Smart impedance matching for high-speed I/O

Patent metadata

Field	Value
Publication number	US-9548734-B1
Application number	US-201514998090-A
Country	US
Kind code	B1
Filing date	Dec 26, 2015
Priority date	Dec 26, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

First claim

What is claimed is:

1. A circuit comprising:
an impedance sensing block;
a finite state machine to provide impedance tuning for a driver; and
a control block, the control block to provide a feedback loop to check and tune impedance of the driver;
wherein the impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of a channel, wherein sampling the output voltage of the driver includes the impedance sensing block to sample a lone rising edge signal; and
wherein the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

2. The circuit of claim 1 , wherein the impedance sensing block is to compare the output voltage of the driver to a reference voltage.

3. The circuit of claim 2 , wherein the reference voltage is half of a voltage swing value for the driver.

4. The circuit of claim 1 , wherein the impedance sensing block is perform multi-point sampling of the output voltage of the driver at multiple points in time or during one or more time durations.

5. The circuit of claim 4 , wherein the impedance sensing block is to process the multi-point sampled output voltage by averaging or weighted-averaging.

6. The circuit of claim 1 , wherein the control block is to sense a data signal and a clock signal for the driver.

7. The circuit of claim 6 , wherein the control block is further to provide a sampling signal based at least in part on the sensing of the data signal and the clock signal for the driver.

8. A method comprising:
sampling an output voltage of a driver driving a signal on a channel, wherein sampling the output voltage of the driver includes sampling a lone rising edge signal;
comparing an impedance of the driver to an impedance of the channel based on the sampling of the output voltage of the driver; and
providing a signal to adjust the impedance of the driver based on the comparison of the impedance of the driver to the impedance of the channel;
wherein the signal to adjust impedance of the driver is either a signal to increase an impedance of the driver if the impedance of the driver is less than an impedance of the channel or a signal to decrease an impedance of the driver if the impedance of the driver is greater than an impedance of the channel.

9. The method of claim 8 , wherein comparing the impedance of the driver to the impedance of the channel includes comparing the output voltage of the driver to a reference voltage.

10. The method of claim 9 , wherein the reference voltage is half of a voltage swing value of the driver.

11. The method of claim 9 , further comprising continuing to compare the impedance of the driver to the impedance of the channel and to provide a signal to adjust impedance of the driver until the comparison of the output voltage of the driver to the reference voltage is within a threshold.

12. The method of claim 8 , wherein sampling an output voltage of the driver includes multi-point sampling at multiple points in time or during one or more certain time durations.

13. The method of claim 12 , further comprising processing the multi-point sampled output voltage by averaging or weighted-averaging.

14. The method of claim 8 , further comprising sensing a data signal and a clock signal for the driver.

15. The method of claim 14 , further comprising providing a sampling signal based at least in part on the sensing of the data signal and the clock signal for the driver.

16. An apparatus comprising:
a driver to drive a signal on a channel;
a variable output resistance;
an impedance sensing logic; and
an impedance matching logic;
wherein the impedance sensing logic is to sample an output voltage of the driver to compare an impedance of the driver to an impedance of the channel, wherein sampling the output voltage of the driver includes the impedance sensing block to sample a lone rising edge signal; and
wherein the impedance matching logic is to adjust the variable output resistance based on the comparison of the impedance of the driver to the impedance of the channel.

17. The apparatus of claim 16 , wherein the comparison of the impedance of the driver to the impedance of the channel includes the impedance sensing logic to compare the output voltage of the driver to a reference voltage.

18. The apparatus of claim 16 , wherein the sample of the output voltage of the driver includes a multi-point sampling at multiple points in time or during one or more certain time durations.

19. The apparatus of claim 18 , wherein the impedance sensing logic is to process the multi-point sampled output voltage by averaging or weighted-averaging.

20. The apparatus of claim 16 , further comprising a controller, the controller to sense a data signal and a clock signal for the driver.

21. The apparatus of claim 20 , wherein the controller is to provide a sampling signal to the impedance sensing logic based at least in part on the sensing of the data signal and the clock signal for the driver.

Assignees

• Song Hongjiang
• Song Yan W
• Qian Zhiguo
• Zhang Zhichao
• Intel Corp

Inventors

• Song Hongjiang
• Song Yan W
• Qian Zhiguo
• Zhang Zhichao

Classifications

• H03K19/017545

  Coupling arrangements; Impedance matching circuits · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title