Magnetoresistive structure having two dielectric layers, and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-9548442-B2
Application number	US-201514797172-A
Country	US
Kind code	B2
Filing date	Jul 12, 2015
Priority date	Sep 30, 2011
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.

First claim

What is claimed is:

1. A method of manufacturing a magnetoresistive device from:
(i) a first electrode, (ii) a first dielectric layer disposed over the first electrode, (iii) a free layer disposed over the first dielectric layer, (iv) a second dielectric layer disposed over the free layer, and (v) a second electrode disposed over the second dielectric layer, the method of manufacturing comprising:
etching through the second electrode and the second dielectric layer to provide a sidewall of (i) the second electrode and (ii) the second dielectric layer;
forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer; and
after forming the encapsulation material on the sidewall of the second electrode and the second dielectric layer, etching through the surface of the free magnetic layer and at least a portion of the first dielectric layer.

2. The method of claim 1 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes depositing silicon nitride or silicon oxide on the sidewall of the second electrode and the second dielectric layer.

3. The method of claim 1 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes:
depositing material on the sidewall of the second electrode and the second dielectric layer, and
after depositing the material, oxidizing the material.

4. The method of claim 3 wherein the material is aluminum or magnesium.

5. The method of claim 1 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes forming silicon nitride or silicon oxide on the sidewall of the second electrode and the second dielectric layer.

6. The method of claim 1 wherein etching through the surface of the free magnetic layer and at least a portion of the first dielectric layer further includes etching through the free magnetic layer and through the first dielectric layer.

7. The method of claim 1 wherein the second electrode is non-ferromagnetic.

8. A method of manufacturing a magnetoresistive device from: (i) a first electrode having one or more layers of ferromagnetic material, (ii) a first dielectric layer disposed on the first electrode, (iii) a free layer disposed on the first dielectric layer, (iv) a second dielectric layer disposed on the free layer, (v) a second electrode disposed on the second dielectric layer, wherein the second electrode is non-ferromagnetic, and (vi) a conductor disposed on the second electrode, the method of manufacturing comprising:
etching through the second electrode and the second dielectric layer to provide sidewalls of (i) the second electrode and (ii) the second dielectric layer;
forming an encapsulation material on the sidewalls of the second electrode and the second dielectric layer; and
after forming the encapsulation material on the sidewalls of the second electrode and the second dielectric layer, etching through the surface of the free magnetic layer.

9. The method of claim 8 wherein forming an encapsulation material on the sidewalls of the second electrode and second dielectric layer includes depositing silicon nitride or silicon oxide on the sidewalls of the second electrode and second dielectric layer.

10. The method of claim 8 wherein forming an encapsulation material on the sidewalls of the second electrode and second dielectric layer includes:
depositing material on the sidewalls of the second electrode and second dielectric layer, and
after depositing the material, oxidizing the material.

11. The method of claim 10 wherein the material is aluminum or magnesium.

12. The method of claim 8 wherein forming an encapsulation material on the sidewalls of the second electrode and second dielectric layer includes forming silicon nitride or silicon oxide on the sidewall of the second electrode and the second dielectric layer.

13. The method of claim 8 wherein etching through the surface of the free magnetic layer further includes etching through a portion of the first dielectric layer.

14. The method of claim 13 wherein etching through at least a portion of the first dielectric layer further includes etching through the first dielectric layer.

15. The method of claim 8 wherein forming an encapsulation material on the sidewalls of the second electrode and second dielectric layer includes forming an encapsulation material having a thickness that, after etching the first dielectric layer, provides a cross-sectional area of the first dielectric layer which is greater than a cross-sectional area of the second dielectric layer.

16. The method of claim 8 wherein forming an encapsulation material on the sidewalls of the second electrode and second dielectric layer includes forming an encapsulation material having a thickness wherein the thickness of the encapsulation material provides a cross-sectional area of the first dielectric layer, after etching the first dielectric layer, which is greater than one and less than five times a cross-sectional area of the second dielectric layer.

Assignees

• Everspin Technologies Inc

Inventors

• Aggarwal Sanjeev
• Nagel Kerry
• Janesky Jason

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/12

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10N50/80

  Constructional details · CPC title