Method for manufacturing and magnetic devices having double tunnel barriers

Patent metadata

Field	Value
Publication number	US-9093640-B2
Application number	US-201414219902-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Sep 30, 2011
Publication date	Jul 28, 2015
Grant date	Jul 28, 2015

Abstract

A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

First claim

What is claimed is:

1. A method of manufacturing a spin-torque magnetoresistive memory element over a substrate, the method comprising:
forming a first electrode over the substrate, wherein the first electrode includes at least one layer of magnetic materials;
forming a first dielectric layer over the first electrode;
forming a free magnetic layer over the first dielectric layer, wherein the free magnetic layer includes a plurality of layers, each layer of the plurality of layers including one or more ferromagnetic materials;
forming a second dielectric layer over a surface of the free magnetic layer;
forming a second electrode over the second dielectric layer, wherein the second electrode includes at least one layer of magnetic materials;
performing a first etch through the second electrode and the second dielectric layer to provide a sidewall of (i) the second electrode and (ii) the second dielectric layer;
forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer; and
after forming the encapsulation material on the sidewall of the second electrode and the second dielectric layer, performing a second etch through the surface of the free magnetic layer.

2. The method of claim 1 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes:
depositing material on the sidewall of the second electrode and the second dielectric layer, and
after depositing the material, oxidizing the material.

3. The method of claim 1 wherein the encapsulation material is aluminum oxide or magnesium oxide.

4. The method of claim 1 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes:
depositing material on the sidewall of the second electrode and the second dielectric layer, wherein the material includes aluminum or magnesium, and
after depositing the material, oxidizing the material.

5. The method of claim 1 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes forming silicon nitride or silicon oxide.

6. The method of claim 1 forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes:
depositing silicon oxide on the sidewall of the second electrode and the second dielectric layer.

7. The method of claim 1 wherein performing a second etch through the surface of the free magnetic layer further includes etching through the free magnetic layer to expose a surface of the first dielectric layer.

8. The method of claim 1 wherein performing a second etch through the surface of the free magnetic layer further includes etching through the free magnetic layer and through a portion of the first dielectric layer to provide a sidewall of the first dielectric layer and to expose a surface of the first dielectric layer.

9. The method of claim 1 wherein performing a second etch through the surface of the free magnetic layer further includes etching through the free magnetic layer and through the first dielectric layer to provide a sidewall of the first dielectric layer and to expose a surface of the first electrode.

10. The method of claim 1 wherein forming a second electrode over the second dielectric layer includes depositing one or more ferromagnetic and/or anti-ferromagnetic layers.

11. The method of claim 1 wherein forming a second electrode over the second dielectric layer includes:
depositing a first ferromagnetic layer over the second dielectric layer,
depositing a coupling layer on the first ferromagnetic layer, and
depositing a second ferromagnetic layer on the coupling layer.

12. The method of claim 11 wherein depositing a coupling layer on the first ferromagnetic layer includes depositing a layer comprising titanium or tantalum.

13. The method of claim 11 wherein depositing a coupling layer on the first ferromagnetic layer includes depositing a layer comprising ruthenium.

14. A method of manufacturing a spin-torque magnetoresistive memory element over a substrate, the method comprising:
forming a first electrode, wherein the first electrode includes a plurality of layers of magnetic materials;
forming a first dielectric layer on the first electrode;
forming a free magnetic element on the first dielectric layer, wherein the free magnetic element includes a plurality of ferromagnetic materials;
forming a second dielectric layer on the free magnetic element;
forming a second electrode on the second dielectric layer;
etching through the second electrode and the second dielectric layer to provide a sidewall of (i) the second electrode and (ii) the second dielectric layer and to expose a surface of the free magnetic element;
forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer; and
after forming the encapsulation material on the sidewall of the second electrode and the second dielectric layer, performing a second etch through the surface of the free magnetic element.

15. The method of claim 14 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes:
depositing material on the sidewall of the second electrode and the second dielectric layer, and
after depositing the material, oxidizing the material.

16. The method of claim 14 wherein the encapsulation material is aluminum oxide or magnesium oxide.

17. The method of claim 14 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes:
depositing material on the sidewall of the second electrode and the second dielectric layer, wherein the material includes aluminum or magnesium, and
after depositing the material, oxidizing the material.

18. The method of claim 14 wherein forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes forming silicon nitride or silicon oxide.

19. The method of claim 14 forming an encapsulation material on the sidewall of the second electrode and the second dielectric layer includes:
depositing silicon on the sidewall of the second electrode and the second dielectric layer, and
after depositing the silicon, oxidizing the silicon.

20. The method of claim 14 wherein performing a second etch through the surface of the free magnetic layer further includes etching through the free magnetic layer to expose a surface of the first dielectric layer.

21. The method of claim 14 wherein performing a second etch through the surface of the free magnetic layer further includes etching through the free magnetic layer and through a portion of the first dielectric layer to provide a sidewall of the first dielectric layer and to expose a surface of the first dielectric layer.

22. The method of claim 14 wherein performing a second etch through the surface of the free magnetic layer further includes etching through the free magnetic layer and through the first dielectric layer to provide a sidewall of the first dielectric layer and to expose a surface of the first electrode.

23. The method of claim 14 wherein forming a second electrode on the second dielectric layer includes depositing one or more ferromagnetic and/or anti-ferromagnetic layers.

24. The method of claim 14 wherein forming a second electrode on the seco

Assignees

• Everspin Technologies Inc

Inventors

• Aggarwal Sanjeev
• Nagel Kerry
• Janesky Jason

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/12 Primary

  Electricity · mapped topic

• H10N50/10

  Magnetoresistive devices · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title