Dual fill silicon-on-nothing field effect transistor

Patent metadata

Field	Value
Publication number	US-9548358-B2
Application number	US-201414280777-A
Country	US
Kind code	B2
Filing date	May 19, 2014
Priority date	May 19, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a substrate. After formation of a first dielectric isolation layer around the patterned stack, a disposable gate structure can be formed. End portions of the second silicon-germanium alloy nanowire are removed to form first cavities underlying end portions of the silicon-containing nanowire. Dielectric nanowires are formed in cavities concurrently with formation of a gate spacer. After recessing the first dielectric isolation layer, a second cavity is formed by removing the first silicon-germanium alloy nanowire. The second cavity is filled with a second dielectric isolation layer, and raised active regions can be formed by a selective epitaxy process. After formation of a planarization dielectric layer, the disposable gate structure and the remaining portion of the second silicon-germanium alloy nanowire with a replacement gate structure.

First claim

What is claimed is:

1. A semiconductor structure comprising:
at least one dielectric isolation layer located on a substrate;
a silicon-containing nanowire containing a source region located at one end of a body region and a drain region located at another end of said body region, said silicon-containing nanowire is located above and spaced apart from said at least one dielectric isolation layer;
a pair of dielectric nanowires laterally spaced from each other, and contacting a bottom surface of said source region and said drain region of said silicon-containing nanowire and a top surface of said at least one dielectric isolation layer; and
a gate structure including a gate dielectric and a gate electrode, said gate structure encircling said body region of said silicon-containing nanowire.

2. The semiconductor structure of claim 1 , wherein said pair of dielectric nanowire is laterally spaced from each other by a portion of said gate structure that is located beneath, and directly contacting, a bottom surface of said body region of said silicon-containing nanowire.

3. The semiconductor structure of claim 2 , wherein a combination of said pair of dielectric nanowires and said portion of said gate structure that is located beneath said body region of said silicon-containing nanowire has a same horizontal cross-sectional area as said silicon-containing nanowire.

4. The semiconductor structure of claim 1 , wherein said at least one dielectric isolation layer comprises:
a first dielectric isolation layer located on a substrate and including at least one rectangular opening therethrough; and
a second dielectric isolation layer contacting a top surface of said first dielectric isolation layer and including a recessed portion that fills said at least one opening.

5. The semiconductor structure of claim 4 , wherein said silicon-containing nanowire is present above, and has a same horizontal cross-sectional area as, said recessed portion of said second dielectric isolation layer.

6. The semiconductor structure of claim 4 , wherein said pair of dielectric nanowires contacts a top surface of said recessed portion.

7. The semiconductor structure of claim 6 , wherein a combination of said pair of dielectric nanowires and said portion of said gate structure that is located beneath said body region of said silicon-containing nanowire has a same horizontal cross-sectional area as said recessed portion.

8. The semiconductor structure of claim 4 , wherein a topmost surface of said first dielectric isolation layer is located between a horizontal plane including a bottommost surface of said second dielectric isolation layer and another horizontal plane including a topmost surface of said second dielectric isolation layer, and a bottommost surface of said first dielectric isolation layer is located below said horizontal plane including said bottommost surface of said second dielectric isolation layer.

9. The semiconductor structure of claim 1 , wherein each of said pair of dielectric nanowires has an end wall that is vertically coincident with an end wall of said silicon-containing nanowire.

10. The semiconductor structure of claim 1 , further comprising a gate spacer laterally surrounding an upper portion of said gate structure and comprising a same dielectric material as said pair of dielectric nanowires.

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L29/66

  Electricity · mapped topic

• H01L29/0673 Primary

  Electricity · mapped topic

• H01L29/0669

  Electricity · mapped topic