Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines

Patent metadata

Field	Value
Publication number	US-9548335-B2
Application number	US-201615171890-A
Country	US
Kind code	B2
Filing date	Jun 2, 2016
Priority date	Nov 10, 2011
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

First claim

What is claimed is:

1. An apparatus, comprising:
a controller; and
an array of resistive memory cells coupled to the controller;
wherein the array of resistive memory cells includes adjacent memory cells selectively electrically separated by a respective isolation device; and
wherein the adjacent memory cells are coupled to a common data line and are formed between two adjacent data line contacts.

2. The apparatus of claim 1 , wherein one memory cell of the adjacent memory cells is configured to receive a signal from a first select line and another memory cell of the adjacent memory cells is configured to receive a signal from a second select line.

3. The apparatus of claim 1 , wherein the array of memory cells includes a number of planar access devices.

4. The apparatus of claim 1 , wherein the array of memory cells includes a number of recessed access devices.

5. The apparatus of claim 1 , wherein the array of memory cells includes a number of fin field effect transistor (FinFET) access devices.

6. An apparatus, comprising:
a controller; and
an array of resistive memory cells coupled to the controller;
wherein the array of resistive memory cells includes a first memory cell selectively electrically separated from a second memory cell by an isolation device; and wherein the first memory cell and second memory cell are coupled to a data line and are formed between a first data line contact and a second data line contact.

7. The apparatus of claim 6 , wherein the second memory cell is coupled to a second select line.

8. The apparatus of claim 6 , wherein the first memory cell is coupled to a first select line.

9. The apparatus of claim 6 , wherein the first memory cell is between the isolation device and a first access device and the second memory cell is between the isolation device and a second access device.

10. The apparatus of claim 6 , wherein an isolation line is coupled to the isolation device.

11. The apparatus of claim 10 , wherein the isolation line is between a storage element of first memory cell and a storage element of the second memory cell.

12. The apparatus of claim 6 , wherein a first word line is between a storage element of the first memory cell and a first data line contact.

13. The apparatus of claim 6 , wherein a second word line is between a storage element of the second memory cell and a second data line contact.

14. An apparatus, comprising:
a controller; and
an array of resistive memory cells coupled to the controller;
wherein the array of resistive memory cells includes a first memory cell selectively electrically separated from a second memory cell by a first isolation device and a third memory cell selectively electrically separated from a fourth memory cell by a second isolation device; and wherein a first data line contact is formed between the second memory cell and the third memory cell.

15. The apparatus of claim 14 , wherein the first, second, third and fourth memory cells are coupled to a data line.

16. The apparatus of claim 14 , wherein the first and third memory cells are coupled to a first select line.

17. The apparatus of claim 14 , wherein the second and fourth memory cells are coupled to a second select line.

18. The apparatus of claim 14 , wherein a first isolation line is between a storage element of first memory cell and a storage element of the second memory cell.

19. The apparatus of claim 14 , wherein a second isolation line is between a storage element of third memory cell and a storage element of the fourth memory cell.

20. The apparatus of claim 14 , wherein the first and second memory cells are formed between the first data contact line and a second data contact line and wherein the third and fourth memory cells are formed between the first data contact line and a third data contact line.

Assignees

• Micron Technology Inc

Inventors

• Liu Zengtao T
• Prall Kirk D
• Violette Mike

Classifications

• G11C13/0021

  Auxiliary circuits · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title