Structure of backside copper metallization for semiconductor devices and a fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9548276-B2
Application number	US-201514868798-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Apr 18, 2012
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.

First claim

What is claimed is:

1. An improved structure of backside copper metallization for semiconductor devices comprising:
a substrate, wherein said substrate is made of GaAs, InP, GaN or SiC;
an active layer formed on a front side of said substrate, wherein said active layer includes at least one integrated circuit;
a backside metal seed layer formed on a backside of said substrate, wherein said backside metal seed layer contains Pd and P;
a high-temperature sustaining buffer layer formed below said backside metal seed layer, wherein said high-temperature sustaining layer is made of Ni alloys, Ni or Ag; and
a backside metal layer formed below said high-temperature sustaining buffer layer, wherein said backside metal layer is made of Cu;
wherein the Pd contained in said backside metal seed layer is uniformly distributed in said backside metal seed layer and the P contained in said backside metal seed layer is uniformly distributed in said backside metal seed layer; and
wherein at high temperature the Pd contained in said backside metal seed layer is distributed closer to said backside of said substrate while the P contained in said backside metal seed layer is distributed closer to said high-temperature sustaining buffer layer, and thereby said high-temperature sustaining buffer layer and the P contained in said backside metal seed layer are mixed at the nearby boundary.

2. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein said high-temperature sustaining buffer layer is made of Ni alloys.

3. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein said high-temperature sustaining buffer layer is made of Ni.

4. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein said high-temperature sustaining buffer layer is made of Ag.

5. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , further comprising at least one oxidation resistant layer, wherein said at least one oxidation resistant layer is formed below said backside metal layer.

6. The improved structure of backside copper metallization for semiconductor devices according to claim 5 , wherein said at least one oxidation resistant layer is selected from the group consisting of Ni, Au, Pd, V, Ni—Au alloys, Ni—Pd alloys, Pd—Au alloys, Ni alloys and Ni—V alloys.

7. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , further comprising at least one via hole, wherein said at least one via hole is formed on said backside of said substrate, an interior surface of said at least one via hole is covered by said backside metal seed layer.

8. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein a thickness of said high-temperature sustaining buffer layer is larger than 10 Å and smaller than 10000 Å.

9. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein a thickness of said high-temperature sustaining buffer layer is larger than 100 Å and smaller than 10000 Å.

10. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein a thickness of said high-temperature sustaining buffer layer is larger than 10 Å and smaller than 9000 Å.

11. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein a thickness of said backside metal seed layer is larger than 10 Å and smaller than 10000 Å.

12. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein a thickness of said backside metal seed layer is larger than 100 Å and smaller than 10000 Å.

13. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein a thickness of said backside metal seed layer is larger than 10 Å and smaller than 9000 Å.

14. The improved structure of backside copper metallization for semiconductor devices according to claim 1 , wherein said substrate is made of GaAs and said high-temperature sustaining buffer layer is made of Ni.

Assignees

• Win Semiconductors Corp

Inventors

• Chen Jason
• Hua Chang-Hwang
• Chu Wen

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/049

  by diffusing alloying elements · CPC title