Test method for memory

Patent metadata

Field	Value
Publication number	US-9548138-B2
Application number	US-201414474382-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Sep 2, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

First claim

What is claimed is:

1. A test method for testing a memory device including a memory array, the memory array including a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines, the test method including:
in testing a first word line of the word lines,
charging a first bit line of the bit lines to test a single bit of a first half of a first symmetric memory cell adjacent to the first bit line; and
charging a second bit line of the bit lines to test a single bit of a second half of a second symmetric memory cell adjacent to the second bit line; and
in testing a second word line of the word lines,
charging the first bit line of the bit lines to test a single bit of the second half of a third symmetric memory cell adjacent to the first bit line; and
charging the second bit line of the bit lines to test a single bit of the first half of a fourth symmetric memory cell adjacent to the second bit line;
wherein in testing each of the word lines, each of the bit lines is charged once.

2. The test method according to claim 1 , wherein in testing the first word line, either one of a first half and a second half of each of the symmetric memory cells on the first word line is read and verified.

3. The test method according to claim 2 , wherein in testing the first word line,
the first halves of about 50% of the symmetric memory cells on the first word line are read and verified; and
the second halves of about the other 50% of the symmetric memory cells on the first word line are read and verified.

4. The test method according to claim 1 , wherein in testing,
first halves of about 50% of the symmetric memory cells on the first bit line are read and verified; and
second halves of about the other 50% of the symmetric memory cells on the first bit line are read and verified.

5. The test method according to claim 1 , wherein
all the symmetric memory cells are grouped into a plurality of pages; and
in verifying, bit lines coupled to one page of the pages are concurrently charged to read and verify the symmetric memory cells of the one page.

6. The test method according to claim 5 , wherein
first halves of about 50% of the symmetric memory cells of the one page are concurrently read and verified; and
second halves of about the other 50% of the symmetric memory cells of the one page are concurrently read and verified.

Assignees

• Macronix Int Co Ltd

Inventors

• Ting Ying-Tsai
• Wu Che-Chin
• Chou Tsung-Yi
• Huang Shih-Fu

Classifications

• G11C17/00

  Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards · CPC title

• G11C29/702

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C2029/1204

  Bit line control · CPC title