Integrated circuit defect detection and repair

Patent metadata

Field	Value
Publication number	US-9548137-B2
Application number	US-201414320164-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Dec 26, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

First claim

What is claimed is:

1. A memory controller for use with a memory having memory cells arranged in rows and columns of memory cells including spare memory cells, comprising:
an internal self-test logic circuit built in within the memory controller, the self-test logic circuit including: a test pattern generator for generating test patterns and for testing memory cells within the memory using the generated test patterns; wherein the test pattern generator includes a plurality of generators including at least one instruction programmable address generator, at least one instruction programmable data generator, and a loop sequencer circuit adapted to apply to the generators a plurality of nested loop instructions, including a sequential loop of address instructions in a sequence of address instructions to the instruction programmable address generator, and to apply to the instruction programmable data generator, a sequential loop of data instructions in a sequence of data instructions nested within the sequential loop of address instructions, wherein the instruction programmable address generator is configured to generate a pattern of memory cell addresses in response to an address instruction being executed in sequence in the loop of address instructions to traverse a memory region of a plurality of memory cells, and wherein each memory cell address includes a row address of row address bits and a column address of column bits and wherein at least one instruction programmable data generator is configured to generate in response to a data instruction being executed in sequence in the loop of data instructions nested within the sequential loop of address instructions, a pattern of data for a pattern of test data, to be written in memory cells addressed by a pattern of memory cell addresses generated by the address generator wherein the generated pattern of data is a selectable function of the pattern of memory cell addresses of the memory cells in which the generated pattern of data is to be written.

2. The memory controller of claim 1 wherein the data generator is configured to invert data in a selectable striped pattern as a function of one of the row address and the column address of the pattern of memory cell addresses of the memory cells in which the generated pattern of data is to be written.

3. The memory controller of claim 1 wherein the data generator is configured to invert data in a selectable checkerboard pattern as a function of the Exclusive-OR function of the lowest order row address bit and lowest order column address bit of the row and column addresses, respectively of the pattern of memory cell addresses of the memory cells in which the generated pattern of data is to be written.

4. The memory controller of claim 1 wherein the data generator is configured to generate a selectable pattern of data which is all logical ones for all memory cell addresses of the memory cells in which the generated pattern of data is to be written.

5. The memory controller of claim 1 wherein the data generator is configured to selectively invert the pattern of data for all memory cell addresses of the memory cells in which the generated pattern of data is to be written.

6. The memory controller of claim 1 wherein the data generator is configured to selectively rotate the generated pattern of data by a bit position for all memory cell addresses of the memory cells in which the generated pattern of data is to be written.

7. The memory controller of claim 6 wherein the data generator is configured to selectively repeat the rotation of a generated pattern of data a bit position a selectable number of times for all memory cell addresses of the memory cells in which the generated pattern of data is to be written.

8. The memory controller of claim 1 wherein the plurality of generators includes at least one address offset generator configured to generate a periodic pattern of memory address offsets as a function of a period and the data generator is configured to provide a selectable periodic data inversion function to selectively invert the pattern of data in a selectable periodic data inversion pattern.

9. The memory controller of claim 8 wherein the data generator is configured to selectively invert the pattern of data in a stripe pattern as a function of the periodic pattern of memory address offsets generated by the address offset generator, wherein the stripe pattern is one of a column stripe, a row stripe, and a diagonal stripe.

10. The memory controller of claim 9 wherein the period of the periodic pattern of memory address offsets is a function of one of the number of rows and the number of columns of the memory cells addressed by the pattern of memory cell addresses generated by the address instruction.

11. The memory controller of claim 8 wherein the period of the periodic pattern of memory address offsets is a function of an initial period and an adjustment to the initial period.

12. The memory controller of claim 11 wherein the initial period is a function of the direction of traversal of the memory cells addressed by the pattern of memory cell addresses generated by the address instruction.

13. The memory controller of claim 11 wherein the initial period is set to one of the number of rows and the number of columns of the memory cells addressed by the pattern of memory cell addresses generated by the address instruction.

14. The memory controller of claim 8 comprising a plurality of data generators chained in a plurality of stages, each data generator configured to generate the pattern of data as a function of memory addresses.

15. The memory controller of claim 14 comprising a plurality of registers adapted to store mapping values, and a logical to physical address mapping logic configured to map logical addresses to physical addresses as a function of the mapping values stored in the registers.

16. A computing device, comprising:
a memory having memory cells arranged in rows and columns of memory cells within the device including spare memory cells;
an internal self-test logic circuit built in within the device, the self-test logic circuit including: a test pattern generator for generating test patterns and for testing memory cells within the memory for defective memory cells using the generated test patterns; wherein the test pattern generator includes a plurality of generators including at least one instruction programmable address generator, at least one instruction programmable data generator, and a loop sequencer circuit adapted to apply to the generators a plurality of nested loop instructions, including a sequential loop of address instructions in a sequence of address instructions to the instruction programmable address generator, and to apply to the instruction programmable data generator, a sequential loop of data instructions in a sequence of data instructions nested within the sequential loop of address instructions, wherein the instruction programmable address generator is configured to generate in response to an address instruction, a pattern of memory cell addresses to traverse a memory region of a plurality of memory cells wherein each memory cell address includes a row address of row address bits and a column address of column bits and wherein, and at least one instruction programmable data generator is configured to generate in response to a data instruction being executed in sequence in the loop of data instructions nested within the sequential loop of address instructions, a pattern of data for a pattern of test data, to be written in memory cells addressed by a pattern of memory cell addres

Assignees

• Intel Corp

Inventors

• Querbach Bruce
• Lui William K
• Ellis David G
• Zimmerman David J
• Schoenborn Theodore Z
• Hampson Christopher W
• Wan Ifar
• Zhang Yulan

Classifications

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/72

  with optimized replacement algorithms · CPC title