System and method for synchronizing networked components

Patent metadata

Field	Value
Publication number	US-9547333-B2
Application number	US-201314051137-A
Country	US
Kind code	B2
Filing date	Oct 10, 2013
Priority date	Oct 10, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.

First claim

What is claimed is:

1. A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, said method comprising:
frequency-locking a plurality of component clocks of the plurality of components to a master clock;
synchronizing to a master counter, driven by the master clock, a plurality of component counters driven by the plurality of component clocks; and
wherein the component clocks, when frequency-locked to the master clock, drive the component counters in synchrony with the master counter, and
frequency-locking comprises encoding a sequence of master clock pulses from the master clock onto a clock stream transmitted among the plurality of components, and at each of the component clocks decoding a sequence of component clock pulses from the clock stream.

2. The method as claimed in claim 1 , wherein encoding a sequence of master clock pulses comprises receiving a master stream at a clock encoder, receiving the sequence of master clock pulses at the clock encoder, and producing the clock stream from the clock encoder by modulating the master stream according to the sequence of master clock pulses.

3. The method as claimed in claim 2 , wherein decoding a sequence of component clock pulses comprises at each component clock receiving the clock stream and demodulating the clock stream to produce the sequence of component clock pulses and to reproduce the master stream.

4. A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, said method comprising:
frequency-locking a plurality of component clocks of the plurality of components to a master clock;
synchronizing to a master counter, driven by the master clock, a plurality of component counters driven by the plurality of component clocks; and
wherein the component clocks, when frequency-locked to the master clock, drive the component counters in synchrony with the master counter, and
synchronizing comprises:
encoding in the clock stream an instruction to set each component counter to match the master counter;
encoding in the clock stream a plurality of instructions for each component to return a plurality of receipt times corresponding to the plurality of instructions;
determining for each of the component counters a correction amount based on the plurality of receipt times returned by the corresponding component; and
encoding in the clock stream an instruction to set each component counter to match the master counter adjusted by the correction amount corresponding to that component counter.

Assignees

• Gen Electric

Inventors

• Breuer Brian
• Woloschek Steven John
• Huffman Nathanael Dale
• Aasen Eric

Classifications

• H04J3/0658

  Clock or time synchronisation among packet nodes · CPC title

• A61B6/566

  involving communication between diagnostic systems · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• A61B6/032

  Transmission computed tomography [CT] · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title