Accurate time capture and transfer between clock domains

Patent metadata

Field	Value
Publication number	US-9547332-B1
Application number	US-201313847736-A
Country	US
Kind code	B1
Filing date	Mar 20, 2013
Priority date	Mar 21, 2012
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A method includes requesting a time maintained in a first clock domain, receiving, in a second clock domain, a first time value from the first clock domain in response to requesting the time maintained in the first clock domain, determining, in the second clock domain, a latency associated at least with receiving the first time value from the first clock domain, and determining a second time value based on the first time value and the determined latency.

First claim

What is claimed is:

1. A method comprising:
sending, to a first clock domain of an integrated circuit (IC) from a second clock domain of the IC, a request signal in response to detecting, at the IC, an event corresponding to a packet being forwarded or transmitted or received, and requiring a time stamp, wherein the request signal indicates a request for a time maintained in the first clock domain;
adjusting, in the first clock domain of the IC, a first time value from the first clock domain to compensate for a first latency caused by synchronizing the request signal to the first clock domain;
receiving, in the second clock domain of the IC, the adjusted first time value from the first clock domain in response to the request signal;
determining, in the second clock domain of the IC, a second latency corresponding to sending the request signal and receiving the first time value associated at least with receiving the first time value from the first clock domain;
calculating a second time value using (i) the adjusted first time value and (ii) the determined second latency; and
using, at the IC, the second time value to generate the time stamp for the packet.

2. A method according to claim 1 , wherein determining the second latency includes determining a value of a counter disposed in the second clock domain.

3. A method according to claim 2 , wherein determining the second latency includes:
resetting the counter in response to detecting the event; and
reading the value of the counter in response to receiving from the first clock domain (i) the first time value or (ii) an indicator that the first time value is available.

4. A method according to claim 3 , wherein calculating the second time value includes adding the value of the counter to the first time value.

5. A method according to claim 1 , wherein:
determining the second latency includes determining a round-trip latency associated at least with requesting a time maintained in the first clock domain and receiving the first time value from the first clock domain; and
calculating the second time value based on (i) the first time value and (ii) the determined second latency includes determining the second time value based on (a) the first time value and (b) the determined round-trip latency.

6. A method according to claim 1 , wherein calculating the second time value includes determining the second time value in the second clock domain.

7. A method according to claim 1 , further comprising:
generating the request signal in the second clock domain,
wherein synchronizing the request signal to the first clock domain includes aligning the request signal to a clock signal of the first clock domain.

8. A method according to claim 7 , wherein synchronizing the request signal to the first clock domain includes:
providing a first output indicating whether the request signal has been detected by a first circuit, wherein providing the first output includes clocking the first circuit using a first clock in the first clock domain;
providing a second output indicating whether the request signal has been detected by a second circuit, wherein providing the second output includes clocking the second circuit using a second clock in the first clock domain, and wherein the second clock is a phase-shifted version of the first clock; and
providing a third output indicating whether the first circuit or the second circuit detected the request signal first;
wherein adjusting the first time value includes using the third output to adjust the first time value.

9. A method according to claim 1 , wherein the time maintained in the first clock domain corresponds to a time of day.

10. An integrated circuit, comprising:
a time tracking circuit disposed in a first clock domain of the integrated circuit;
a time request generator disposed in a second clock domain of the integrated circuit and configured to request a time maintained by the time tracking circuit in response to detecting an event corresponding to a packet being forwarded or transmitted or received, and requiring a time stamp;
a first latency compensator circuit configured to adjust a first time value from the time tracking circuit to compensate for a first latency caused by synchronizing a request signal from the time request generator to the first clock domain;
a latency determination circuit disposed in the second clock domain and configured to determine a latency associated at least with sending the request signal to the first clock domain and receiving the first time value from the time tracking circuit;
a second latency compensator circuit configured to calculate a second time value using the adjusted first time value and the determined latency; and
a logic circuit configured to generate a time stamp for the packet using the second time value.

11. An integrated circuit according to claim 10 , further comprising a counter disposed in the second clock domain, and wherein the latency determination circuit is configured to determine the latency at least in part by determining a value of the counter.

12. An integrated circuit according to claim 11 , wherein the latency determination circuit is configured to determine the latency at least in part by:
resetting the counter in response to detecting the event; and
reading the value of the counter in response to receiving from the first clock domain (i) the first time value or (ii) an indicator that the first time value is available.

13. An integrated circuit according to claim 12 , wherein the second latency compensator circuit is configured to calculate the second time value at least in part by adding the value of the counter to the first time value.

14. An integrated circuit according to claim 10 , wherein:
the time request generator is configured to request the time maintained by the time tracking circuit at least in part by generating the request signal;
the integrated circuit further comprises a synchronization circuit disposed in the first clock domain and configured to synchronize the request from the second clock domain to the first clock domain, wherein the synchronization circuit includes:
a first circuit configured to provide a first output indicating whether the request signal has been detected, wherein the first circuit is clocked using a first clock generated in the first clock domain,
a second circuit configured to provide a second output indicating whether the request signal has been detected, wherein the second circuit is clocked using a second clock generated in the first clock domain, and wherein the second clock is a phase-shifted version of the first clock, and
a third circuit coupled to the first output and the second output, wherein the third circuit is configured to provide a third output indicating whether the first circuit or the second circuit detected the request signal first.

15. A method for obtaining a time maintained in a first clock domain of an integrated circuit (IC), the method comprising:
generating a request signal in a second clock domain of the IC in response to detecting, at the IC, an event corresponding to a packet being forwarded or transmitted or received, and requiring a time stamp;
converting the request signal from the second clock domain to the first clock domain; providing, in the first clock domain, a first time value in response to the converted request signal;
calculating, in the first clock domain, a second time value by adjusting the first time value to compensate for a latency associated at least with converting the request signal from the second clock domain to the first clock domain;
generating

Assignees

• Marvell Israel (M I S L) Ltd

Inventors

• Mizrahi Tal

Classifications

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H04J3/0682

  by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging · CPC title

• H04J3/0697

  Synchronisation in a packet node · CPC title