Dynamically measuring power consumption in a processor

Patent metadata

Field	Value
Publication number	US-9547027-B2
Application number	US-201213996266-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	Mar 30, 2012
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores to independently execute instructions;
a first sensor to measure a first power consumption level of the processor based at least in part on a plurality of events that occur on the plurality of cores; and
a first logic to combine the first power consumption level and a second power consumption level of the processor determined based on a value of a dynamic current provided to the processor, wherein the first logic is to execute a low power load on the processor and calculate the first and second power consumption levels using sensor information from the first sensor and the dynamic current, respectively, determine and store an offset based on the first and second power consumption levels, execute a high power load on the processor and calculate the second power consumption level using the dynamic current, determine and store a slope based on the offset and the calculated second power consumption level, and determine the combined power consumption level using another second power consumption level, the slope and the offset.

2. The processor of claim 1 , further comprising a power controller to control at least one of an operating frequency and a voltage of the processor based on the combined first and second power consumption levels and a power limit of the processor.

3. The processor of claim 1 , wherein the first sensor comprises a logic to receive counter information from a plurality of event counters associated with each of the plurality of cores and to measure the first power consumption level based on the counter information.

4. The processor of claim 1 , wherein the first logic is to combine the first power consumption level and the second power consumption level by:
generation of a first correction factor using the first power consumption level and the second power consumption level; and
generation of a second correction factor using the second power consumption level and the first correction factor.

5. The processor of claim 4 , wherein the first logic is to determine the combined power consumption level using the second power consumption level and the first and second correction factors.

6. A method comprising:
receiving, in a first logic of a processor, sensor information from a digital power meter of the processor, and calculating a first power consumption level of the processor using the sensor information from the digital power meter;
receiving, in the first logic, sensor information from a current sensor adapted to measure a current delivered by a voltage regulator coupled to the processor, and calculating a second power consumption level of the processor using the sensor information from the current sensor, including:
executing a low power load on the processor and calculating the first and second power consumption levels using the sensor information from the digital power meter and the sensor information from the current sensor, respectively, and determining and storing an offset based on the first and second power consumption levels; and
executing a high power load on the processor and calculating the second power consumption level using the sensor information from the current sensor, and determining and storing a slope based on the offset and the calculated second power consumption level; and
combining, in the first logic, the first power consumption level and another second power consumption level to obtain a hybrid power consumption level of the processor, using the another second power consumption level, the slope and the offset.

7. The method of claim 6 , further comprising controlling at least one of an operating frequency and a voltage of the processor based on the hybrid power consumption level and a power limit of the processor.

8. The method of claim 7 , wherein combining the first and second power consumption levels comprises:
if the first power consumption level is less than a threshold, using the first power consumption level to control the at least one of the operating frequency and the voltage; and
otherwise, using the second power consumption level to control the at least one of the operating frequency and the voltage.

9. The method of claim 7 , wherein combining the first and second power consumption levels comprises:
generating a first correction factor using the first power consumption level and the second power consumption level; and
generating a second correction factor using the second power consumption level and the first correction factor.

10. The method of claim 9 , further comprising determining the hybrid power consumption level using the second power consumption level and the first and second correction factors.

11. The method of claim 10 , further comprising controlling at least one of an operating frequency and a voltage of the processor based on the hybrid power consumption level.

12. A system comprising:
a multicore processor including a plurality of cores to independently execute instructions, each of the plurality of cores including at least one event counter to count events that occur on the core, a digital power meter to calculate a first power consumption level based on information from the event counters, a second power meter to calculate a second power consumption level based on information regarding a current delivered to the multicore processor from a voltage regulator, and a power controller including a first logic to generate a combined power consumption level of the multicore processor using the first and second power consumption levels, wherein the first logic is to cause a low power load level to occur on the multicore processor and calculate the first and second power consumption levels during the low power load level, determine and store an offset based on first and second power consumption levels, cause a high power load level to occur on the multicore processor and calculate the second power consumption level during the high power load level, determine and store a slope based on the offset and the calculated second power consumption level, and determine the combined power consumption level using another second power consumption level, the slope and the offset;
the voltage regulator coupled to the multicore processor to provide a regulated voltage to the multicore processor, the voltage regulator including a current sensor to provide the information regarding the current delivered to the multicore processor; and
a dynamic random access memory (DRAM) coupled to the multicore processor.

13. The system of claim 12 , wherein the first logic is to receive the second power consumption level during normal operation of the system.

14. A processor comprising:
a plurality of execution units each to independently execute instructions;
a first sensor to measure a first power consumption level of the processor based at least in part on a plurality of events that occur on the plurality of execution units;
a logic to combine the first power consumption level and a second power consumption level of the processor determined based on information regarding a dynamic current provided to the processor, the information obtained from a current sensor coupled to the processor to measure the dynamic current, wherein the logic is to:
cause a low power load level to occur on the processor, calculate the first and second power consumption levels during the low power load level, and determine and store an offset based on first and second power consumption levels; and
cause a high power load level to occur on the processor, calculate the second power consumption level during the high power load level, determine and store

Assignees

• Varma Ankush
• Sistla Krishnakanth V
• Rowland Martin T
• Garg Vivek
• Burns James S
• Intel Corp

Inventors

• Varma Ankush
• Sistla Krishnakanth V
• Rowland Martin T
• Garg Vivek
• Burns James S

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic