Wiring substrate and method for manufacturing wiring substrate

Patent metadata

Field	Value
Publication number	US-9545016-B2
Application number	US-201514675819-A
Country	US
Kind code	B2
Filing date	Apr 1, 2015
Priority date	Apr 21, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A wiring substrate includes an insulating layer, and a connection terminal formed on the insulating layer. The connection terminal includes a metal layer formed on the insulating layer and including an upper surface, a metal post formed on the upper surface of the metal layer and including upper and side surfaces, and a surface plating layer that covers the upper and side surfaces of the metal post. The metal layer includes a material that is inactive with respect to a material included in the surface plating layer. The metal layer has an upper surface edge part that is exposed at an outside from the side surface of the metal post in a plan view. The surface plating layer is formed to expose the upper surface edge part of the metal layer.

First claim

What is claimed is:

1. A wiring substrate comprising:
an insulating layer; and
a connection terminal formed on the insulating layer;
wherein the connection terminal includes
a metal layer formed on the insulating layer and including an upper surface,
a metal post formed on the upper surface of the metal layer and including upper and side surfaces, and
a surface plating layer that covers the upper and side surfaces of the metal post,

wherein the metal layer includes a material that is inactive with respect to a material included in the surface plating layer,
wherein the metal layer has an upper surface edge part that is exposed at an outside from the side surface of the metal post in a plan view,
wherein the surface plating layer is formed to expose the upper surface edge part of the metal layer, and
wherein a space or spaces are formed in an area where an inner peripheral surface of the upper surface edge part and an end part of a surface of the surface plating layer face other.

2. The wiring substrate as claimed in claim 1 , wherein the metal layer is formed of a material that has a lower affinity with respect to solder compared to the surface plating layer.

3. The wiring substrate as claimed in claim 1 , wherein an adhesive strength between the metal post and the surface plating layer is greater than an adhesive strength between the metal layer and the surface plating layer.

4. The wiring substrate as claimed in claim 1 ,
wherein the insulating layer includes a projecting part, and
wherein the connection terminal is formed on the projecting part.

5. A wiring substrate comprising:
an insulating layer; and
a connection terminal formed on the insulating layer;
wherein the connection terminal includes
a metal layer formed on the insulating layer and including upper and side surfaces,
a metal post formed on the upper surface of the metal layer and including upper and side surfaces, and
a surface plating layer that covers the upper and side surfaces of the metal post,

wherein the metal layer includes a material that is inactive with respect to a material included in the surface plating layer,
wherein the metal layer has an upper surface edge part that is exposed at an outside from the side surface of the metal post in a plan view,
wherein the surface plating layer is formed to cover the upper surface edge part and the side surface of the metal layer and
wherein a space or spaces are formed in an area where an inner peripheral surface of the upper surface edge part and an end part of a surface of the surface plating layer face other.

6. The wiring substrate as claimed in claim 5 , wherein the metal layer is formed of a material that has a lower affinity with respect to solder compared to the surface plating layer.

7. The wiring substrate as claimed in claim 5 , wherein an adhesive strength between the metal post and the surface plating layer is greater than an adhesive strength between the metal layer and the surface plating layer.

8. The wiring substrate as claimed in claim 5 ,
wherein the insulating layer includes a projecting part, and
wherein the connection terminal is formed on the projecting part.

Assignees

• Shinko Electric Ind Co

Inventors

• Imafuji Kei
• Shimizu Noriyoshi
• Ol Kiyoshi
• Arisaka Hiromu

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H05K3/3436

  having an array of bottom contacts, e.g. pad grid array or ball grid array components · CPC title

• H05K3/244

  Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465) · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K3/4007 Primary

  Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465) · CPC title