Method and apparatus for data aided timing recovery in 10GBASE-T system

Patent metadata

Field	Value
Publication number	US-9544128-B2
Application number	US-201314768302-A
Country	US
Kind code	B2
Filing date	Feb 21, 2013
Priority date	Feb 21, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method of data-aided timing recovery for Ethernet systems is disclosed. A first device negotiates a pseudorandom number sequence with a second device and receives a data signal from the second device. The first device samples the received data signal to recover a first training sequence. The first device also generates a second training sequence based on the pseudorandom number sequence. The second training sequence is then synchronized with the first training sequence. The synchronized second training sequence is used to align a receive clock signal of the first device with the data signal received from the second device.

First claim

What is claimed is:

1. A method of timing recovery performed by a first device, the method comprising:
negotiating a pseudorandom number sequence with a second device;
sampling a data signal received from the second device to recover a first training sequence;
generating a second training sequence based on the pseudorandom number sequence;
synchronizing the second training sequence with the first training sequence by comparing the first training sequence with the second training sequence and iteratively adjusting the second training sequence based on the comparing, wherein comparing the first training sequence with the second training sequence comprises:
determining a peak correlation between the first training sequence and the second training sequence by comparing each bit of the first training sequence with two or more bits of the second training sequence over a threshold number of data cycles, wherein the peak correlation is based on a number of matching bits within the first training sequence and the second training sequence and further based on a degree of variation between adjacent bits of the pseudorandom number sequence; and

aligning a receive clock signal of the first device with the received data signal using the synchronized second training sequence.

2. The method of claim 1 , wherein iteratively adjusting the second training sequence comprises:
incrementing an address pointer that generates the second training sequence if no peak correlation is detected after the threshold number of data cycles.

3. The method of claim 1 , wherein the second training sequence is synchronized with the first training sequence when the peak correlation is detected.

4. The method of claim 1 , wherein the receive clock signal is to sample the data signal received from the second device.

5. A method of timing recovery performed by a first device, the method comprising:
negotiating a pseudorandom number sequence with a second device;
sampling a data signal received from the second device to recover a first training sequence;
generating a second training sequence based on the pseudorandom number sequence;
synchronizing the second training sequence with the first training sequence; and
aligning a receive clock signal of the first device with the received data signal using the synchronized second training sequence, wherein aligning the receive clock signal comprises determining a timing error between the first training sequence and the synchronized second training sequence and adjusting the receive clock signal based on the timing error.

6. The method of claim 5 , wherein the timing error comprises a Mueller-Muller timing error.

7. The method of claim 5 , wherein determining the timing error comprises:
generating an error signal corresponding to the timing error between the first training sequence and the synchronized second training sequence.

8. The method of claim 7 , further comprising:
filtering the error signal using a loop filter; and
adjusting one or more parameters of the loop filter to limit jitter in the receive clock signal.

9. The method of claim 8 , wherein adjusting one or more parameters of the loop filter comprises:
decreasing a value of the one or more parameters of the loop filter after a threshold amount of time has elapsed.

10. The method of claim 1 , wherein recovering the first training sequence further comprises:
mitigating intersymbol interference in the received data signal using feed-forward equalization.

11. A non-transitory computer-readable storage medium configured to store program instructions that, when executed by a processor of a first device, cause the first device to:
negotiate a pseudorandom number sequence with a second device;
sample a data signal received from the second device to recover a first training sequence;
generate a second training sequence based on the pseudorandom number sequence;
synchronize the second training sequence with the first training sequence by comparing the first training sequence with the second training sequence; and iteratively adjusting the second training sequence based on the comparing, wherein comparing the first training sequence with the second training sequence comprises:
determining a peak correlation between the first training sequence and the second training sequence by comparing each bit of the first training sequence with two or more bits of the second training sequence over a threshold number of data cycles, wherein the peak correlation is based on a number of matching bits within the first training sequence and the second training sequence and further based on a degree of variation between adjacent bits of the pseudorandom number sequence; and

align a receive clock signal of the first device with the received data signal using the synchronized second training sequence.

12. The non-transitory computer-readable storage medium of claim 11 , wherein execution of the program instructions to iteratively adjust the second training sequence cause the first device to:
increment an address pointer used to generate the second training sequence if no peak correlation is detected after the threshold number of data cycles.

13. The non-transitory computer-readable storage medium of claim 11 , wherein the second training sequence is synchronized with the first training sequence when the peak correlation is detected.

14. The non-transitory computer-readable storage medium of claim 11 , wherein the receive clock signal is used to sample the data signal received from the second device.

15. A non-transitory computer-readable storage medium configured to store program instructions that, when executed by a processor of a first device, cause the first device to:
negotiate a pseudorandom number sequence with a second device;
sample a data signal received from the second device to recover a first training sequence;
generate a second training sequence based on the pseudorandom number sequence;
synchronize the second training sequence with the first training sequence; and
align a receive clock signal of the first device with the received data signal using the synchronized second training sequence, wherein aligning the receive clock signal comprises determining a timing error between the first training sequence and the synchronized second training sequence, and adjusting the receive clock signal based on the timing error.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the timing error comprises a Mueller-Muller timing error.

17. The non-transitory computer-readable storage medium of claim 15 , wherein execution of the program instructions to determine the timing error cause the first device to:
generate an error signal corresponding to the timing error between the first training sequence and the synchronized second training sequence.

18. The non-transitory computer-readable storage medium of claim 17 , further comprising program instructions that cause the first device to:
filter the error signal; and
adjust one or more parameters of a loop filter to limit jitter in the receive clock signal.

19. A device, comprising:
a processor to negotiate a pseudorandom number sequence with another device;
an analog-to-digital converter (ADC) to sample a data signal received from the other device to recover a first training sequence;
a training sequence generator to generate a second training sequence based on the pseudorandom number sequence;
a data synchronization circuit to synchronize the second training sequence with the first

Assignees

• Qualcomm Inc

Inventors

• Jiang Hai
• Huang Yin
• Xu Changlong
• Li Jian
• Xue Yisheng

Classifications

• H04L7/043

  Pseudo-noise [PN] codes variable during transmission (synchronisation of spread spectrum receivers H04B1/69) · CPC title

• H04L7/0037 Primary

  Delay of clock signal · CPC title

• H04L7/10

  Arrangements for initial synchronisation · CPC title

• H04L7/0062 Primary

  detection of error based on data decision error, e.g. Mueller type detection · CPC title