Flip-flop-based clock deskew circuit

Patent metadata

Field	Value
Publication number	US-9197397-B1
Application number	US-201414329272-A
Country	US
Kind code	B1
Filing date	Jul 11, 2014
Priority date	Jul 11, 2014
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

A clock deskew circuit for transferring data from a first clock domain to a second clock domain. This circuit includes a data path, which has: a transmitter latch controlled by a transmitter clock in a first clock domain; a receiver latch controlled by a receiver clock in a second clock domain; and an intermediate latch coupled between the transmitter latch and the receiver latch. The transmitter clock and the receiver clock have an unknown phase offset. The circuit additionally includes a control circuit coupled between the transmitter clock and the receiver clock, and generates a control clock for the immediate latch based on the transmitter clock and the receiver clock. The control circuit selects between a first operation mode and a second operation mode for the data path circuit based at least on the phase relationship of the control clock with respect to the transmitter clock and the receiver clock.

First claim

What is claimed is:

1. A clock deskew circuit for safely transferring data from a first clock domain to a second clock domain, comprising:
a data path circuit, comprising:
a transmitter latch controlled by a transmitter clock in a first clock domain;
a receiver latch controlled by a receiver clock in a second clock domain, wherein the transmitter clock and the receiver clock have an unknown phase offset; and
an intermediate latch coupled between the transmitter latch and the…

Assignees

• Oracle Int Corp

Inventors

• Ono Tarik
• Yang Suwen
• Greenstreet Mark R

Classifications

• G06F1/10

  Physics · mapped topic

• G06F1/12

  Physics · mapped topic

• H04L7/0045

  Electricity · mapped topic

• H04L7/0037 Primary

  Electricity · mapped topic

• H04L7/0012 Primary

  Electricity · mapped topic