Diode-based devices and methods for making the same

Patent metadata

Field	Value
Publication number	US-9543472-B2
Application number	US-201514983138-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Apr 9, 2007
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

First claim

What is claimed is:

1. A method comprising:
forming a dielectric layer on a first substrate, the first substrate comprising a first crystalline semiconductor material, a first opening and a second opening each being through the dielectric layer and exposing the first crystalline semiconductor material;
forming a first bottom diode region by growing a first portion of a second crystalline semiconductor material in and extending out of the first opening;
forming a second bottom diode region by growing a second portion of a second crystalline semiconductor material in and extending out of the second opening;
forming a first active diode region on the first bottom diode region, and a second active diode region on the second bottom diode region, the first active diode region being physically separated from the second active diode region;
forming a continuous top diode region on the first active diode region and the second active diode region;
bonding a second substrate to the continuous top diode region;
removing the first substrate;
forming a first contact on the second substrate; and
forming a second contact on the dielectric layer and the second crystalline semiconductor material.

2. The method of claim 1 , wherein the each of the first portion and the second portion of the second crystalline semiconductor material has a pyramidal shape extending out of the first opening and the second opening, respectively.

3. The method of claim 1 , wherein second crystalline semiconductor material is lattice mismatched to the first crystalline semiconductor material, threading dislocations in the first portion of the second crystalline semiconductor material arising from the lattice mismatch with the first crystalline semiconductor material terminating in the first opening, threading dislocations in the second portion of the second crystalline semiconductor material arising from the lattice mismatch with the first crystalline semiconductor material terminating in the second opening.

4. The method of claim 1 , wherein an aspect ratio of the first opening is at least 1.

5. The method of claim 1 , wherein the continuous top diode region has a planar surface distal the first active diode region and the second active diode region.

6. The method of claim 5 , wherein the second substrate is bonded to the planar surface of the continuous top diode region.

7. The method of claim 1 , wherein the first and second openings are holes.

8. A method comprising:
depositing a layer of a dielectric material over a first substrate, the first substrate comprising a first crystalline semiconductor material, the dielectric material having a dielectric surface distal from the first substrate;
patterning a first opening in the dielectric material to expose a first portion of the first substrate, the first opening being through the dielectric surface of the dielectric material;
forming a first bottom diode region by growing a second crystalline semiconductor material in and above the first opening, the first bottom diode region having a first sidewall surface extending above and away from the dielectric surface of the dielectric material;
forming a first active diode region directly adjacent the first sidewall surface of the first bottom diode region, the first active diode region having a second sidewall surface extending above and away from the dielectric surface of the dielectric material;
patterning a second opening in the dielectric material to expose a second portion of the first substrate;
forming a second bottom diode region by growing the second crystalline semiconductor material in and above the second opening;
forming a second active diode region adjacent the second bottom diode region, the second active diode region having a third sidewall surface extending above and away from the dielectric surface of the dielectric material;
forming a top diode region directly adjacent the second sidewall surface of the first active diode region and the third sidewall surface of the second active diode region, the top diode region physically separating the second sidewall surface of the first active diode region from the third sidewall surface of the second active diode region above the dielectric surface of the dielectric material;
bonding a second substrate to the top diode region; and
removing the first substrate.

9. The method of claim 8 , wherein the first bottom diode region is fin shaped extending out of the first opening.

10. The method of claim 8 , wherein second crystalline semiconductor material is lattice mismatched to the first crystalline semiconductor material, threading dislocations in the first portion of the second crystalline semiconductor material arising from the lattice mismatch with the first crystalline semiconductor material terminating in the first opening.

11. The method of claim 8 , wherein the first opening has an aspect ratio of at least 1.

12. The method of claim 8 , wherein the first active diode region contains multiple quantum wells.

13. The method of claim 8 , wherein the second crystalline semiconductor material comprises a material selected from the group consisting essentially of a Group III-V compound, a Group II-VI compound, and a Group IV alloy.

14. The method of claim 8 , wherein the first opening is a trench.

15. The method of claim 8 , wherein the first substrate is selected from the group consisting of silicon, sapphire, and silicon carbide.

16. A method comprising:
patterning a first trench in a dielectric layer to expose a first portion of a first substrate, the first substrate comprising a first crystalline semiconductor material, the first trench having an aspect ratio of at least 1;
forming a first fin as first bottom diode region by growing a second crystalline semiconductor material that is lattice mismatched to the first crystalline semiconductor material in and above the first trench, the first fin having a first sidewall and a second sidewall extending above and away from the dielectric layer;
forming a first active diode region directly adjacent the first fin, the first active diode region having a second sidewall surface extending above and away from the dielectric layer, the first active diode region extending along the first sidewall, the second sidewall, and a top surface of the first fin;
forming a top diode region directly adjacent the second sidewall surface of the first active diode region;
bonding a second substrate to the top diode region; and
removing the first substrate.

17. The method of claim 16 further comprising:
patterning a second trench in the dielectric layer to expose a second portion of the first substrate;
forming a second fin as a second bottom diode region by growing the second crystalline semiconductor material in and above the second trench; and
forming a second active diode region adjacent the second fin, wherein the top diode region is formed laterally adjacent the second active diode region.

18. The method of claim 16 , wherein the second crystalline semiconductor material comprises a material selected from the group consisting essentially of a Group III-V compound, a Group II-VI compound, and a Group IV alloy.

19. The method of claim 8 further comprising:
forming a first contact on the second substrate; and
forming a second contact on the dielectric material and the second crystalline semiconductor material.

20. The method of claim 16 further comprising:
forming a first contact on the second substrate; and
forming a second contact on

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lochtefeld Anthony J

Classifications

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/276

  Lateral overgrowth · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title