Vertical junction FinFET device and method for manufacture

Patent metadata

Field	Value
Publication number	US-9543304-B2
Application number	US-201514677404-A
Country	US
Kind code	B2
Filing date	Apr 2, 2015
Priority date	Apr 2, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

First claim

What is claimed is:

1. An integrated circuit transistor device, comprising:
a semiconductor substrate;
a region within the semiconductor substrate doped with a first conductivity-type dopant;
a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the first conductivity-type dopant;
a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant; and
a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with a second conductivity-type dopant.

2. The integrated circuit transistor device of claim 1 , wherein the first conductivity-type dopant is n-type and the second conductivity-type dopant is p-type.

3. The integrated circuit transistor device of claim 1 , wherein the first conductivity-type dopant is p-type and the second conductivity-type dopant is n-type.

4. The integrated circuit transistor device of claim 1 , wherein a dopant concentration of the region within the semiconductor substrate exceeds a dopant concentration of the fin of semiconductor material.

5. The integrated circuit transistor device of claim 1 , wherein a dopant concentration of the second epitaxial region exceeds a dopant concentration of the fin of semiconductor material.

6. The integrated circuit transistor device of claim 1 , further comprising a layer of insulating material on top of the region within the semiconductor substrate which isolates a bottom portion of said fin from bottom portions of adjacent fins.

7. The integrated circuit transistor device of claim 1 , wherein the integrated circuit transistor device is a junction field effect transistor (JFET) device with said second epitaxial region comprising a gate structure, said region within the semiconductor substrate comprising a source region and said first epitaxial region comprising a drain region.

8. The integrated circuit transistor device of claim 1 , wherein the first epitaxial region is formed of a semiconductor material selected from the group consisting of silicon, silicon-germanium and silicon-carbide.

9. The integrated circuit transistor device of claim 1 , wherein the second epitaxial region is formed of a semiconductor material.

10. An integrated circuit, comprising:
a semiconductor substrate;
a first region within the semiconductor substrate doped with a first conductivity-type dopant;
a second region within the semiconductor substrate doped with a second conductivity-type dopant;
a first fin of semiconductor material having a first end in contact with said first region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said first fin doped with the first conductivity-type dopant;
a second fin of semiconductor material having a first end in contact with said second region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said second fin doped with the second conductivity-type dopant;
a first epitaxial region in contact with the second end of the first fin of semiconductor material, said first epitaxial region doped with the first conductivity-type dopant;
a second epitaxial region in contact with the second end of the second fin of semiconductor material, said second epitaxial region doped with the second conductivity-type dopant;
a third epitaxial region in contact with sidewalls of the first fin of semiconductor material, said third epitaxial region doped with the second conductivity-type dopant; and
a fourth epitaxial region in contact with sidewalls of the second fin of semiconductor material, said fourth epitaxial region doped with the first conductivity-type dopant.

11. The integrated circuit of claim 10 , wherein the first region, first fin, first epitaxial region and third epitaxial region form a first vertical junction field effect transistor of a first polarity type, and wherein the second region, second fin, second epitaxial region and fourth epitaxial region form a second vertical junction field effect transistor of a second polarity type that is complementary of the first polarity type.

12. The integrated circuit of claim 10 , wherein a dopant concentration of the first region within the semiconductor substrate exceeds a dopant concentration of the first fin of semiconductor material, and a dopant concentration of the second region within the semiconductor substrate exceeds a dopant concentration of the second fin of semiconductor material.

13. The integrated circuit of claim 10 , wherein a dopant concentration of the first epitaxial region exceeds a dopant concentration of the first fin of semiconductor material, and a dopant concentration of the second epitaxial region exceeds a dopant concentration of the second fin of semiconductor material.

14. The integrated circuit of claim 10 , wherein the first, second, third and fourth epitaxial regions are each formed of a semiconductor material selected from the group consisting of silicon, silicon-germanium and silicon-carbide.

15. An integrated circuit transistor device, comprising:
a semiconductor substrate;
a region within the semiconductor substrate doped with an n-type conductivity-type dopant;
a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the n-type conductivity-type dopant;
a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the n-type conductivity-type dopant; and
a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with a p-type conductivity-type dopant;
wherein the region, fin, first epitaxial region and second epitaxial region form a vertical junction field effect transistor.

16. An integrated circuit transistor device, comprising:
a semiconductor substrate;
a region within the semiconductor substrate doped with a p-type conductivity-type dopant;
a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the p-type conductivity-type dopant;
a first epitaxial region in contact with the second end of the fin of semiconductor material, said first epitaxial region doped with the p-type conductivity-type dopant; and
a second epitaxial region in contact with sidewalls of the fin of semiconductor material, said second epitaxial region doped with an n-type conductivity-type dopant;
wherein the region, fin, first epitaxial region and second epitaxial region form a vertical junction field effect transistor.

17. An integrated circuit transistor device, comprising:
a semiconductor substrate;
a region within the semiconductor substrate doped with a first conductivity-type dopant;
a fin of semiconductor material having a first end in contact with said region within the semiconductor substrate and having a second end and having sidewalls between said first and second ends, said fin doped with the first conductivity-type dopant;
a first epitaxial region in contact with the second end of the fin of semiconductor material, s

Assignees

• St Microelectronics Inc

Inventors

• Liu Qing
• Zhang John Hongguang

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L21/283

  Electricity · mapped topic

• H01L29/1066

  Electricity · mapped topic

• H01L29/66893

  Electricity · mapped topic

• H01L29/7832

  Electricity · mapped topic