Vertical source/drain junctions for a finFET including a plurality of fins

Patent metadata

Field	Value
Publication number	US-8969963-B2
Application number	US-201213650176-A
Country	US
Kind code	B2
Filing date	Oct 12, 2012
Priority date	Oct 12, 2012
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Fin-defining mask structures are formed over a semiconductor material layer. A semiconductor material portion is formed by patterning the semiconductor material layer, and a disposable gate structure is formed over the fin-defining mask structures. After formation of a disposable template layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed by etching center portions of the semiconductor material portion employing the combination of the disposable template layer and the fin-defining mask structures as an etch mask. A first pad region and a second pad region laterally contact the plurality of semiconductor fins. A replacement gate structure is formed on the plurality of semiconductor fins. The disposable template layer is removed, and the first pad region and the second pad regions are vertically recessed. Vertical source/drain junctions can be formed by introducing dopants through vertical sidewalls of the recessed source and second pad regions.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a contiguous semiconductor portion located on an insulator layer, said contiguous semiconductor portion including:
a first pad portion;
a second pad portion spaced from said first pad portion;
a plurality of semiconductor fins connecting said first pad portion and said second pad portion,
wherein a source region includes said first pad portion and first end portions of said plurality of semiconductor fins, and a d…

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Leobandung Effendi
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H10D30/62 Primary

  Electricity · mapped topic

• H10D30/024 Primary

  Electricity · mapped topic