Semiconductor device with discrete blocks

Patent metadata

Field	Value
Publication number	US-9543278-B2
Application number	US-201514886775-A
Country	US
Kind code	B2
Filing date	Oct 19, 2015
Priority date	Sep 10, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
providing a die;
providing a connection block having an integrated passive device and one or more conductive elements extending from a first side of the connection block to a second side of the connection block;
forming a layer comprising the die and the connection block separated by a material layer, the connection block being formed of a material different from that of the material layer; and
planarizing the integrated passive device with the connection block, the die, and the material layer.

2. The method of claim 1 , wherein the planarizing the integrated passive device further comprises performing a chemical mechanical polishing process.

3. The method of claim 1 , wherein the integrated passive device comprises at least one trench capacitor.

4. The method of claim 1 , wherein the layer comprises a molding compound.

5. The method of claim 1 , further comprising forming a first interconnect layer over a first side of the die and the connection block.

6. The method of claim 5 , further comprising forming a second interconnect layer over a second side of the die and the connection block opposite the first side of the die and the connection block.

7. A method of manufacturing a semiconductor device, the method comprising:
placing a connection block separated from a semiconductor die, wherein the connection block comprises an integrated passive device and through substrate vias, the through substrate vias extending from a first side of the connection block to a second side of the connection block;
encapsulating the connection block and the semiconductor die with an encapsulant; and
planarizing the encapsulant, the semiconductor die, and the integrated passive device.

8. The method of claim 7 , further comprising forming a redistribution layer in connection with the connection block and the semiconductor device.

9. The method of claim 8 , further comprising forming a metallization layer on an opposite side of the connection block from the redistribution layer.

10. The method of claim 9 , wherein the planarizing the encapsulant, the semiconductor die, and the integrated passive device further comprises performing a chemical mechanical polishing process.

11. The method of claim 7 , wherein the connection block comprises silicon oxide.

12. The method of claim 7 , wherein the through substrate vias have a pitch of about 60 μm.

13. The method of claim 7 , wherein the integrated passive device is a trench capacitor.

14. The method of claim 7 , wherein the encapsulant is a molding compound.

15. The method of claim 7 , wherein the integrated passive device is formed in a metallization layer of the connection block.

16. A method of manufacturing a semiconductor device, the method comprising:
placing a semiconductor die onto a carrier;
placing a connection block onto the carrier, wherein the connection block is laterally removed from the semiconductor die, the connection block further comprising:
integrated passive devices; and
vias that extend from a first side of the connection block to a second side of the connection block;

encapsulating the semiconductor die and the connection block with an encapsulant while the semiconductor die and the connection block are on the carrier; and
grinding the encapsulant until the encapsulant, the integrated passive devices and the semiconductor die are planar with each other.

17. The method of claim 16 , further comprising forming a redistribution layer to electrically connect the semiconductor die and the connection block after the grinding the encapsulant.

18. The method of claim 17 , further comprising forming a metallization layer on an opposite side of the connection block from the redistribution layer after the forming the redistribution layer.

19. The method of claim 16 , wherein the connection block comprises silicon oxide that extends from a first surface of the connection block to a second surface of the connection block opposite the first surface, wherein the first surface faces the carrier after the placing the connection block onto the carrier.

20. The method of claim 16 , wherein the vias have a pitch of about 60 μm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsiao Ching-Wen
• Chen Chen-Shien
• Chang Wei Sen
• Hu shou-cheng

Classifications

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title