Designs and methods for conductive bumps

Patent metadata

Field	Value
Publication number	US-9543261-B2
Application number	US-97361510-A
Country	US
Kind code	B2
Filing date	Dec 20, 2010
Priority date	Sep 22, 2003
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

First claim

What is claimed is:

1. An assembly comprising:
a die;
a package having a first side facing a surface of the die and an opposing second side;
a pad disposed on the die, the pad including aluminum;
a base layer metal disposed on the pad, the base layer including titanium;
a bump disposed directly on the base layer metal (BLM), the bump including copper;
a first solder layer disposed on the bump, the first solder layer including tin and having a first material composition; and
a second solder layer disposed on the first side of the package, the second solder layer including tin and having a second material composition different from the first material composition;
wherein the first solder layer on the bump and the second solder layer on the package form an interconnect electrically coupling and attaching the die with the package.

2. The assembly of claim 1 , wherein the base layer metal (BLM) further includes copper.

3. The assembly of claim 1 , wherein the first solder layer further includes silver.

4. The assembly of claim 1 , wherein the second solder layer on the package further includes silver and copper.

5. The assembly of claim 1 , further comprising a diffusion barrier layer disposed between the bump and the first solder layer.

6. The assembly of claim 5 , further comprising a wetting layer disposed between the diffusion barrier layer and the first solder layer.

7. The assembly of claim 5 , wherein the diffusion barrier layer includes phosphorous.

8. The assembly of claim 1 , wherein the assembly is substantially free of lead.

Assignees

• Dubin Valery M
• Balakrishnan Sridhar
• Bohr Mark
• Intel Corp

Inventors

• Dubin Valery M
• Balakrishnan Sridhar
• Bohr Mark

Classifications

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title

• H10W72/251

  Materials · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title