Segmented bond pads and methods of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9543260-B2
Application number	US-201313958276-A
Country	US
Kind code	B2
Filing date	Aug 2, 2013
Priority date	Aug 2, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first bond pad disposed at a first side of a substrate, the first bond pad comprising a first plurality of conductive pad segments, wherein each of the conductive pad segment of the first plurality of conductive pad segments is electrically isolated from the remaining conductive pad segments of the first plurality of pad segments, wherein one of the first plurality of conductive pad segments is larger in area than the remaining conductive pad segments of the first plurality of conductive pad segments, and wherein top surfaces of all of the plurality of conductive pad segments are coplanar.

2. The device of claim 1 , further comprising a second bond pad spaced from the first bond pad disposed at the first side, the second bond pad comprising a second plurality of conductive pad segments, wherein at least one pad segment of the second plurality of conductive pad segments is electrically isolated from the remaining conductive pad segments of the second plurality of conductive pad segments.

3. The device of claim 2 , wherein the first bond pad is coupled to a source node of a transistor, and wherein the second bond pad is coupled to a gate node of the transistor.

4. The device of claim 2 , wherein the first bond pad is coupled to a drain node of a transistor, and wherein the second bond pad is coupled to a gate node of the transistor.

5. The device of claim 1 , wherein each of the first plurality of conductive pad segments is separated from an adjacent conductive pad segment of the first plurality of conductive pad segments by a plurality of openings.

6. The device of claim 5 , wherein the plurality of openings comprise a dielectric material.

7. The device of claim 1 , wherein the semiconductor device comprises a discrete semiconductor device.

8. The device of claim 1 , wherein the semiconductor device comprises an integrated circuit.

9. The device of claim 1 , wherein the first bond pad is a solder pad.

10. The device of claim 1 , wherein the first plurality of pad segments comprises quadrilateral shaped pad segments arranged on a first plane in a direction inclined to a major edge of the first bond pad, wherein the first plane is parallel to a major surface of the first bond pad.

11. The device of claim 1 , wherein the first plurality of pad segments comprise hexagonal shaped pad segments.

12. The device of claim 1 , wherein the first plurality of pad segments comprise a ball bond configuration having concentric segments around a center region as viewed on a first plane, wherein the first plane is parallel to a major surface of the first bond pad.

13. A semiconductor device comprising:
a first bond pad disposed at a first side of a substrate, the first bond pad comprising a first portion and a second portion comprising a first plurality of conductive pad segments, wherein the first portion of the first bond pad is electrically coupled to the substrate, wherein the second portion of the first bond pad is electrically isolated from the substrate, wherein a contact area of the first portion is larger than a contact area of each of pad segments of the second portion, and wherein a top surface of the first portion and a top surface of the second portion are coplanar.

14. The device of claim 13 , wherein the first and the second portions of the first bond pad are configured to be coupled to a first common external interconnect.

15. The device of claim 13 , wherein at least one pad segment of the first plurality of conductive pad segments is electrically isolated from the remaining pad segments of the first plurality of conductive pad segments.

16. The device of claim 15 , wherein each of the first plurality of conductive pad segments is separated from an adjacent pad segment of the first plurality of conductive pad segments by a plurality of openings.

17. The device of claim 16 , wherein the plurality of openings comprise a dielectric material.

18. The device of claim 13 , further comprising a second bond pad spaced from the first bond pad disposed at the first side, the second bond pad comprising a first portion and a second portion, wherein the first portion of the second bond pad is electrically coupled to the substrate, and wherein the second portion of the second bond pad is electrically isolated from the substrate.

19. The device of claim 18 , wherein at least one pad segment of the first plurality of conductive pad segments is electrically isolated from the remaining pad segments of the first plurality of conductive pad segments, wherein the second portion of the second bond pad comprises a second plurality of conductive pad segments, wherein at least one pad segment of the second plurality of conductive pad segments is electrically isolated from the remaining pad segments of the second plurality of conductive pad segments.

20. The device of claim 13 , wherein the first plurality of conductive pad segments comprise quadrilateral shaped pad segments arranged on a plane parallel to a major surface of the first bond pad and in a direction inclined to a major edge of the first bond pad, or wherein the first plurality of conductive pad segments comprise hexagonal shaped pad segments, or wherein the first portion includes edges and sidewalls shaped to align with hexagonal shaped pad segments, or wherein the plurality of pad segments comprise a ball bond configuration having concentric segments arranged around a center region comprising the first portion.

21. A semiconductor device comprising:
a semiconductor chip having a first side;
a first bond pad disposed at the first side of the semiconductor chip, the first bond pad comprising a first portion comprising a single pad segment and a second portion, the second portion comprising a first plurality of conductive pad segments, wherein a pad segment of the first plurality of conductive pad segments is electrically isolated from the remaining pad segments of the first plurality of conductive pad segments and electrically isolated from the single pad segment of the first portion; and
a first external interconnect contacting the first portion of the first bond pad, wherein a pad segment of the first plurality of conductive pad segments is electrically coupled to the single pad segment of the first portion only through the first external interconnect.

22. The device of claim 21 , wherein the first external interconnect contacts the pad segment of the first plurality of conductive pad segments.

23. The device of claim 21 , wherein the first external interconnect comprises a wire bond, a clip, or a ribbon.

24. The device of claim 21 , further comprising:
a second bond pad spaced from the first bond pad disposed at the first side, the second bond pad comprising a first portion and a second portion comprising a second plurality of conductive pad segments, wherein at least one pad segment of the second plurality of conductive pad segments is electrically isolated from the remaining pad segments of the second plurality of conductive pad segments; and
a second external interconnect contacting the first portion of the second bond pad.

25. The device of claim 24 , wherein the first external interconnect comprises a wire bond and the second external interconnect comprises a clip.

26. The device of claim 21 , wherein the first plurality of conductive pad segments comprise quadrilateral shaped pad segments arranged on a

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut
• Zigldrum Matthias

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/751

  of bond wires · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title