Preventing over-polishing of poly gate in metal-gate CMP

Patent metadata

Field	Value
Publication number	US-9543212-B2
Application number	US-201514663389-A
Country	US
Kind code	B2
Filing date	Mar 19, 2015
Priority date	May 26, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device that includes a first gate in a first-type transistor region and a second gate in a second-type transistor region, forming an interlayer dielectric layer on the semiconductor substrate, and planarizing the interlayer dielectric layer to expose the surface of the first and second gates. The method also includes forming a hard mask layer on the second gate, removing the first gate using the hard mask layer as a mask to form a trench, forming sequentially a work function metal layer and a metal gate layer in the trench, and removing a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer to form a metal gate.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising a front-end device, the front-end device comprising a first gate in a first type transistor region and a second gate in a second type transistor region;
forming an interlayer dielectric layer on the semiconductor substrate;
performing a first chemical mechanical polishing (CMP) process having a removal rate of the first and second gates higher than a removal rate of the interlayer dielectric layer on the interlayer dielectric layer so that a surface of the first gate and a surface of the second gate are below a surface of the interlayer dielectric layer after the first CMP process;
removing a portion of the second gate so that the second gate is lower than the interlayer dielectric layer;
forming a hard mask layer on the first gate, the second gate, and the interlayer dielectric layer;
removing a portion of the hard mask layer disposed on the first type transistor region;
removing the first gate by etching using the hard mask layer as a mask to form a trench;
forming a first work function metal layer in the trench and on the hard mask layer over the second gate;
forming a first metal gate layer on the first work function metal layer;
forming a metal gate by performing a second CMP process to remove a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer; and
removing a portion of the first work function metal layer, a portion of the metal gate layer, and a portion of the hard mask layer over the second gate to expose the second gate.

2. The method of claim 1 , wherein removing the portion of the second gate comprises removing a portion of the first gate so that the first gate and the second gate have a height (thickness) less than a height (thickness) of the interlayer dielectric layer.

3. The method of claim 2 , wherein removing the portion of the first gate and the portion of the second gate comprises performing a CMP process that has a removal rate of the first and second gates higher than a removal rate of the interlayer dielectric layer.

4. The method of claim 1 , wherein the portion of the second gate being removed has a thickness in a range between 20 Angstroms and 80 Angstroms.

5. The method of claim 1 , wherein the first gate and the second gate comprise polysilicon.

6. The method of claim 1 , wherein, after the first CMP process, the first gate, the second gate, and the interlayer dielectric layer are coplanar.

7. The method of claim 1 , wherein the hard mask layer comprises titanium nitride.

8. The method of claim 1 , wherein forming the hard mask layer comprises a deposition process.

9. The method of claim 1 , wherein the metal gate layer comprises aluminum or aluminum alloy.

10. The method of claim 1 , further comprising:
performing a third CMP process to expose a surface of the second gate.

11. The method of claim 10 , wherein the third CMP process stops when the surface of the second gate is exposed.

12. The method of claim 10 , further comprising, after the third CMP process:
Removing the second gate by etching to form a second trench;
forming a second work function metal layer in the second trench; and
forming a second metal gate layer on the second work function metal layer.

13. The method of claim 1 , wherein the first type transistor region comprises a P-type metal gate transistor, and the second type transistor region comprises an N-type metal gate transistor.

14. The method of claim 1 , wherein the first type transistor region comprises an N-type metal gate transistor, and the second type transistor region comprises a P-type metal gate transistor.

15. The method of claim 1 , wherein the first type transistor region comprises a P-type metal gate transistor, and the second type transistor region comprises a polysilicon transistor.

16. The method of claim 1 , wherein the first type transistor region comprises an N-type metal gate transistor, and the second type transistor region comprises a polysilicon transistor.

17. An electronic device comprising an electronic component and a semiconductor device electrically connected with the electronic component, the semiconductor device being fabricated by a process comprising the steps of:
providing a semiconductor substrate containing a front-end device, the front-end device comprising a first gate in a first type transistor region and a second gate in a second type transistor region;
forming an interlayer dielectric layer on the semiconductor substrate;
performing a first chemical mechanical polishing (CMP) process having a removal rate of the first and second gates higher than a removal rate of the interlayer dielectric layer on the interlayer dielectric layer so that a surface of the first gate and a surface of the second gate are below a surface of the interlayer dielectric layer after the first CMP process;
removing a portion of the second gate so that the second gate is lower than the interlayer dielectric layer;
forming a hard mask layer on the first gate, the second gate and the interlayer dielectric layer;
removing a portion of the hard mask layer disposed on the first type transistor region;
removing the first gate by etching using the hard mask layer as a mask to form a trench;
forming a first work function metal layer in the trench and on the hard mask layer over the second gate;
forming a metal gate layer on the first work function metal layer; and
forming a metal gate by performing a second CMP process to remove a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer.

18. A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising a front-end device, the front-end device comprising a first gate in a first type transistor region and a second gate in a second type transistor region, the first and second gates comprising a polysilicon material, the second gate being wider than the first gate;
forming an interlayer dielectric layer on the semiconductor substrate;
performing a first chemical mechanical polishing (CMP) process on the interlayer dielectric layer to expose a surface of the first gate and a surface of the second gate;
performing a second CMP process having a removal rate of the first and second gates higher than a removal rate of the interlayer dielectric layer, thereby causing the surface of the first gate and second gate being lower than the surface of the interlayer dielectric layer;
forming a hard mask layer on the first gate, the second gate, and the interlayer dielectric layer;
removing a portion of the hard mask layer disposed on the first type transistor region;
removing the first gate by etching using the hard mask layer as a mask to form a trench;
forming a first work function metal layer in the trench and on the hard mask layer over the second gate;
forming a first metal gate layer on the first work function metal layer; and
forming a metal gate by performing a third CMP process to remove a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer, the third CMP process has a high removal rate for the metal gate layer and for the first work function metal layer than for the interlayer dielectric layer, thereby leaving a portion of the first work function metal layer and a porti

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zhu Pulei
• Jiang Li
• Li Xiantao

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01314

  the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L21/82345 Primary

  Electricity · mapped topic