Method and apparatus for selecting data path elements for cloning

Patent metadata

Field	Value
Publication number	US-9542523-B2
Application number	US-201214424220-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Sep 14, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method and apparatus for selecting data path elements for cloning within an integrated circuit (IC) design is described. The method comprises performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.

First claim

The invention claimed is:

1. A method of selecting data path elements for cloning within an integrated circuit (IC) design, the method comprising:
performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path;
calculating at least one annotated delay value for cloning a candidate element within the at least one data path;
calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value;
validating the cloning of the candidate element based at least partly on the at least one modified slack value; and
fabricating the IC design based at least on the validated cloning of the candidate element.

2. The method of claim 1 , wherein the method further comprises:
identifying at least one timing critical path comprising a negative slack value; and
selecting the candidate element for cloning from the at least one timing critical path comprising a negative slack value.

3. The method of claim 2 , wherein the method comprises:
identifying a timing critical path comprising a worst negative slack value; and
selecting the candidate element for cloning from the at least one timing critical path comprising the worst negative slack value.

4. The method of claim 1 , wherein calculating the at least one annotated delay value for cloning the candidate element comprises calculating at least one from a group comprising:
an annotated delay value for a driving data path of the candidate element representative of an additional load of a clone element to be driven;
a negative annotated delay value for at least one timing critical data path driven by the candidate element representative of a reduced load for a first candidate clone element when driving the at least one timing critical data path;
a negative annotated delay value for at least one timing critical data path driven by the candidate element representative of a reduced element size for the first candidate clone element when driving the at least one timing critical data path;
a negative annotated delay value for at least one timing non-critical data path driven by the candidate element representative of a reduced load for a second candidate clone element when driving the at least one timing non-critical data path; and
a negative annotated delay value for at least one timing non-critical data path driven by the candidate element representative of a reduced element size for the second candidate clone element when driving the at least one timing non-critical data path.

5. The method of claim 1 , wherein the method comprises:
calculating at least one modified slack value for each data path comprising a candidate stage; and
validating the cloning of the candidate element based at least partly on the modified slack values for all of the data paths comprising the candidate stage.

6. The method of claim 1 , where the method comprises:
identifying a timing critical path comprising a worst negative slack value;
selecting a candidate element for cloning from the at least one timing critical path comprising a worst negative slack value;
calculating at least one modified slack value for each data path comprising the candidate stage in accordance with the at least one calculated annotated delay value;
determining a new worst negative slack value; and
validating the cloning of the candidate element if the new worst negative slack value for modified slack values is less than the worst negative slack value for unmodified slack values.

7. The method of claim 1 , wherein the method comprises;
identifying timing critical paths comprising negative slack values; and
incrementally validating at least one candidate element within each identified timing critical path comprising a negative slack value.

8. The method of claim 7 , wherein the method comprises:
incrementally validating at least one candidate element within each identified timing critical path comprising a negative slack value starting with a timing critical path comprising a worst negative slack value and sequentially progressing through the identified timing critical paths from the timing critical path comprising a worst negative slack value through to the timing critical path comprising a least negative slack value.

9. The method of claim 1 , wherein the method further comprises assessing a suitability of each stage of the at least one data path for cloning.

10. The method of claim 9 , wherein the method comprises sequentially selecting candidate elements from stages identified as being suitable for cloning, starting at a capture end of the at least one data path and stepping back up towards a launch end of the at least one data path.

11. The method of claim 9 , wherein assessing the suitability of a stage of the at least one data path for cloning comprises determining whether the stage fulfils at least one criteria from a group comprising:
an output load of the stage being greater than an output load threshold value;
an output of the stage comprising a fan-out greater than one; and
an output wire load of the stage exceeding a combined load of driven cells by more than a delta threshold value.

12. The method of claim 11 , wherein the method comprises identifying a stage of the at least one data path as a candidate stage for buffer insertion if an output wire load of said stage exceeds a combined load of driven cells by more than a delta threshold value.

13. The method of claim 11 , wherein the method comprises identifying a stage of the at least one data path as a candidate stage for distance reduction between itself and at least one stage driven thereby if at least one criterion is met from a group comprising:
an output of said stage comprises a fan-out of one; and
an output wire load of said stage exceed a combined load of driven cells by more than a delta threshold value.

Assignees

• Priel Michael
• Berkovitz Asher
• Fleshel Slavaf
• Grinshpon Amir
• Kuzmin Dan
• Miller Yoav
• Freescale Semiconductor Inc

Inventors

• Priel Michael
• Berkovitz Asher
• Fleshel Slavaf
• Grinshpon Amir
• Kuzmin Dan
• Miller Yoav

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5031

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic