Adjustable over-restrictive cache locking limit for improved overall performance

Patent metadata

Field	Value
Publication number	US-9542325-B2
Application number	US-201615212899-A
Country	US
Kind code	B2
Filing date	Jul 18, 2016
Priority date	Dec 23, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Disclosed is a multi-core processor that includes a processor core, a graphics core, and a cache controller. The cache controller receives a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in a cache. The cache controller sends, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device. The cache controller receives a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache. The cache controller locks the way in the second set in response to the second request.

First claim

What is claimed is:

1. A multi-core processor comprising:
a processor core;
a graphics core; and
a cache controller coupled to the processor core and the graphics core, the cache controller to:
receive a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in a cache;
send, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device;
receive a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache; and
lock the way in the second set in response to the second request.

2. The multi-core processor of claim 1 , wherein the cache is a set-associative cache that comprises the first set and the second set, wherein each of the first set and the second set comprises a plurality of lockable ways that each correspond to a set of memory addresses.

3. The multi-core processor of claim 1 , wherein the cache is a set-associative cache comprising a plurality of sets of ways.

4. The multi-core processor of claim 3 , wherein the cache controller is further to determine a lock limit to indicate a maximum number of lockable ways for each of the plurality of sets of ways.

5. The multi-core processor of claim 4 , wherein the cache controller is further to adjust the lock limit for each of the plurality of sets of ways.

6. The multi-core processor of claim 4 , wherein the cache controller is further to increment a rejection counter in response to determining that the way in the first set is not lockable for the I/O device.

7. The multi-core processor of claim 6 , wherein the cache controller is further to:
determine that the rejection counter is above a rejection threshold in response to sending the rejection of the first request;
determine that the lock limit is below a maximum lock value; and
increment the lock limit.

8. The multi-core processor of claim 4 , wherein the cache controller is further to:
send a message to the I/O device that indicates that the second request has been granted;
increment a grant counter when the second request has been granted; and
decrement the lock limit when the grant counter exceeds a grant threshold.

9. The multi-core processor of claim 1 , wherein the cache controller is further to:
send a recommendation in the rejection of the first request for the I/O device to cancel the lock of the first address and to send the second request for a replacement address; and
receive an indication from the I/O device to cancel the lock of the first address in connection with receipt of the second request.

10. A system comprising:
main memory;
an input-output (I/O) device;
a cache; and
a processor coupled to the cache, the I/O device, and the main memory, the processor comprising a cache controller to:
receive a first request from the I/O device to lock a first address that corresponds to a first way in the cache;
determine that the first way in the cache is not lockable for the I/O device;
send, to the I/O device, a rejection of the first request;
receive a second request from the I/O device to lock a second address that corresponds to a second way in the cache; and
lock the second way in the cache in response to the second request.

11. The system of claim 10 , wherein the cache is a set-associative cache that comprises a plurality of lockable ways that each correspond to a set of memory addresses, wherein the plurality of lockable ways comprises the first way and the second way.

12. The system of claim 11 , wherein the set-associative cache comprises a plurality of sets of ways, wherein a first set of ways comprises the first way, and wherein a second set of ways comprises the second way.

13. The system of claim 12 , the cache controller further to determine a lock limit to indicate a maximum number of lockable ways for each of the plurality of lockable ways that may be locked for the device.

14. The system of claim 13 , wherein the lock limit is a same dynamically adjustable value for each of the plurality of sets of ways.

15. The system of claim 13 , the cache controller further to increment a reject counter in response to determining that the first way in the cache is not lockable for the device.

16. The system of claim 15 , the cache controller further to:
determine that the reject counter is above a rejection threshold in response to sending the rejection of the first request;
determine that the lock limit is below a maximum lock value; and
increment the lock limit.

17. The system of claim 13 , wherein when locking the second way in the cache in response to the second request, the cache controller is to:
send a message to the device that indicates that the second request has been granted; and
increment a grant counter,
wherein the cache controller is further to decrement the lock limit when the grant counter exceeds a grant threshold.

18. The system of claim 10 , wherein when sending, to the device, the rejection of the first request, the cache controller is to:
lock the first way of the cache, wherein the rejection to the request comprises a recommendation for the device to cancel the lock and to send the second request; and
receive an indication from the device to cancel the lock of the first way and the second request.

19. A system comprising:
main memory;
an input-output (I/O) device;
a cache; and
a processor coupled to the cache, the I/O device, and the main memory, the processor comprising a cache controller to:
receive a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in the cache;
send, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device;
receive a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache; and
lock the way in the second set in response to the second request.

20. The system of claim 19 , wherein the cache is a set-associative cache that comprises the first set and the second set, wherein each of the first set and the second set comprises a plurality of lockable ways that each correspond to a set of memory addresses.

Assignees

• Intel Corp

Inventors

• Greenspan Daniel
• Majumder Supratik

Classifications

• G06F2212/6082

  Way prediction in set-associative cache · CPC title

• G06F12/1466

  Key-lock mechanism · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F2212/6032

  Way prediction in set-associative cache · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title