Electronic system with memory control mechanism and method of operation thereof
US-2015363312-A1 · Dec 17, 2015 · US
Cache memory for hybrid disk drives
US9104580B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9104580-B1 |
| Application number | US-201113069406-A |
| Country | US |
| Kind code | B1 |
| Filing date | Mar 23, 2011 |
| Priority date | Jul 27, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
Official abstract text for this publication.
A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for data storage, comprising: in a data storage system that includes a main storage device and a non-volatile memory, assessing a respective quality level of each memory block of a plurality of memory blocks of the non-volatile memory; identifying a first subset of memory blocks of the plurality of memory blocks, wherein the quality level of each memory block of the first subset of memory blocks is less than a predefined quality threshold;…
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- G06F12/0871Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9104580B1 cover?
- A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache m…
- Who is the assignee on this patent?
- Meir Avraham, Apple Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0871. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).