System and method for error-minimizing voltage threshold selection

Patent metadata

Field	Value
Publication number	US-9542258-B1
Application number	US-201313842771-A
Country	US
Kind code	B1
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Embodiments of solid-state storage devices provided herein include a voltage threshold calculation mechanism to calculate an optimal voltage read threshold for minimizing read errors. The system may be configured to determine optimal reference voltage value(s) by interpolating a pair of reads at two different threshold levels to determine the point that generates the least number of errors. In some cases, the evaluation may be an approximation based on a Cumulative Distribution Function (CDF) of errors of a first type and a second type. In other cases, the evaluation may be a calculation of an optimal voltage threshold based on the CDF of the errors. In yet other cases, the evaluation may be based on the Probability Density Function (PDF) of the errors.

First claim

What is claimed is:

1. A method for determining voltage thresholds in a memory device of a non-volatile memory array, the memory device comprising one or more memory cells, the method comprising:
performing a first read operation of the memory device using a first voltage threshold to obtain a first plurality of values;
identifying, in the first plurality of values, a first number of bit errors of a first type and a first number of bit errors of a second type;
performing a second read operation of the memory device using a second voltage threshold to obtain a second plurality of values, the second voltage threshold being different from the first voltage threshold;
identifying, in the second plurality of values, a second number of bit errors of the first type and a second number of bit errors of the second type;
performing a first linear interpolation process based on the first and second number of bit errors of the first type, the first voltage threshold, and the second voltage threshold;
performing a second linear interpolation process based on the first and second number of bit errors of the second type, the first voltage threshold, and the second voltage threshold; and
determining an error-minimizing voltage threshold that reduces bit errors during reads of the memory device based, at least in part, on the first linear interpolation process and the second linear interpolation process,
wherein the method is performed under control of a controller.

2. The method of claim 1 , further comprising setting a reference value of the memory device to the error-minimizing voltage threshold.

3. The method of claim 2 , wherein each memory cell of the memory device comprises a single-level cell with one state selection threshold, the one state selection threshold set to the reference value.

4. The method of claim 2 , wherein each memory cell of the memory device comprises a multi-level cell with at least three state selection thresholds, and wherein a first state selection threshold of the at least three state selection thresholds comprises the reference value and is associated with a Low-page for the memory device, and a second state selection threshold and a third state selection threshold of the at least three state selection thresholds are associated with an Up-page for the memory device.

5. The method of claim 1 ,
wherein the first linear interpolation process is associated with a first cumulative distribution function and the second linear interpolation process is associated with a second cumulative distribution function, and
wherein determining the error-minimizing voltage threshold comprises determining an approximation of the error-minimizing voltage threshold by determining an intersection of the first cumulative distribution function based on the first and second number of bit errors of the first type, and the second cumulative distribution function based on the first and second number of bit errors of the second type.

6. The method of claim 1 ,
wherein the first linear interpolation process is associated with a first cumulative distribution function and the second linear interpolation process is associated with a second cumulative distribution function, and
wherein determining the error-minimizing voltage threshold comprises determining a voltage point where a summation of bit errors of the first type and bit errors of the second type is minimum based on the first cumulative distribution function based on the first and second number of bit errors of the first type, and the second cumulative distribution function based on the first and second number of bit errors of the second type.

7. The method of claim 1 , wherein:
identifying the first numbers of bit errors of the first and second types comprises using an Error-Correcting Code (ECC) process on the first plurality of values to identify a number of bits set to a first state that should be set to a second state and a number of bits set to the second state that should be set to the first state; and
identifying the second numbers of bit errors of the first and second types comprises using the ECC process on the second plurality of values to identify a number of bits set to the first state that should be set to the second state and a number of bits set to the second state that should be set to the first state.

8. A method for determining voltage thresholds in a memory device of a non-volatile memory array, the memory device comprising one or more memory cells, the method comprising:
performing a Low-page read operation of the memory device using a Low-page voltage reference threshold to obtain a first plurality of values;
performing a first Up-page read operation of the memory device using a first voltage threshold and a second voltage threshold to obtain a second plurality of values;
identifying, in a first subset of bits of the second plurality of values, a first number of bit errors of a first type and a first number of bit errors of a second type, wherein the first subset of bits of the second plurality of values are identified based on corresponding bits of the first plurality of values that are set to a first state;
identifying, in a second subset of bits of the second plurality of values, a second number of bit errors of the first type and a second number of bit errors of the second type, wherein the second subset of bits of the second plurality of values are identified based on corresponding bits of the first plurality of values that are set to a second state;
performing a second Up-page read operation of the memory device using a third voltage threshold and a fourth voltage threshold to obtain a third plurality of values;
identifying, in a first subset of bits of the third plurality of values, a third number of bit errors of the first type and a third number of bit errors of the second type, wherein the first subset of bits of the third plurality of values are identified based on corresponding bits of the first plurality of values that are set to the first state;
identifying, in a second subset of bits of the third plurality of values, a fourth number of bit errors of the first type and a fourth number of bit errors of the second type, wherein the second subset of bits of the third plurality of values are identified based on corresponding bits of the first plurality of values that are set to the second state;
performing a first linear interpolation process based on the first voltage threshold, the first number of bit errors of the first type, the first number of bit errors of the second type, the third voltage threshold, the third number of bit errors of the first type, and the third number of bit errors of the second type;
determining a first error-minimizing voltage threshold that reduces bit errors in the first subset of bits of the second plurality of values and the first subset of bits of the third plurality of values during reads of the memory device based, at least in part, on the first linear interpolation process; and
determining a second error-minimizing voltage threshold that reduces bit errors in the second subset of bits of the second plurality of values and the second subset of bits of the third plurality of values during reads of the memory device based, at least in part, on the second voltage threshold, the second number of bit errors of the first type, the second number of bit errors of the second type, the fourth voltage threshold, the fourth number of bit errors of the first type, and the fourth number of bit errors of the second type,
wherein the method is performed under control of a controller.

9. The method of claim 8 , further comprising, at least one of:
setting a first reference value of the memory device to the first error-minimizin

Assignees

• Western Digital Tech Inc

Inventors

• Lu Guangming
• Zhao Dengtao

Classifications

• G06F11/1072 Primary

  in multilevel memories · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title