System-on-chip and application processor including FIFO buffer and mobile device comprising the same

Patent metadata

Field	Value
Publication number	US-9542152-B2
Application number	US-201314086083-A
Country	US
Kind code	B2
Filing date	Nov 21, 2013
Priority date	Nov 27, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.

First claim

What is claimed is:

1. A system-on-chip comprising:
a data producer;
a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer;
a first consumer which pops out data of a memory area corresponding to a first read pointer of the FIFO buffer; and
a second consumer which pops out data of a memory area corresponding to a second read pointer of the FIFO buffer,
wherein the FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer, wherein if the difference between the second read pointer and the write pointer corresponds to the size of the FIFO buffer and the difference between the first read pointer and the write pointer is more than a first threshold value and less than a second threshold value, the FIFO buffer request a pop-out operation by the second consumer.

2. The system-on-chip of claim 1 , wherein the first consumer is a functional block consuming data in real time and the second consumer consumes data in non-real time.

3. The system-on-chip of claim 1 , wherein if the difference between the second read pointer and the write pointer corresponds to the size of the FIFO buffer and the difference between the first read pointer and the write pointer is less than a first threshold value, the FIFO buffer overwrites data from the data producer at a memory area corresponding to the second read pointer.

4. The system-on-chip of claim 3 , wherein the FIFO buffer informs the second consumer that the overwritten data is invalid data.

5. The system-on-chip of claim 1 , wherein the FIFO buffer requests that the data producer stops generating data.

6. The system-on-chip of claim 1 , wherein the FIFO buffer comprises:
a memory which has an input port receiving data provided from the data producer and a plurality of output ports outputting data to the first and second consumers; and
FIFO control logic which generate the write pointer and the first and second read pointers and determines the status of the FIFO buffer related to the first and second consumers by referring to the write pointer and the first and second read pointers.

7. The system-on-chip of claim 6 , wherein if the difference between the second read pointer and the write pointer corresponds to the size of the FIFO buffer and the difference between the first read pointer and the write pointer is less than a first threshold value, the FIFO control logic controls the memory to forcibly overwrite data from the data producer at a memory area corresponding to the second read pointer.

8. The system-on-chip of claim 7 , wherein if the difference between the second read pointer and the write pointer corresponds to the size of the FIFO buffer and the difference between the first read pointer and the write pointer is more than a first threshold value and less than a second threshold value, the FIFO control logic generates a flag signal requesting a pop-out operation of the second consumer.

9. The system-on-chip of claim 6 , wherein the FIFO control logic comprises:
a write pointer generator which generates a write pointer in response to data push from the data producer;
a first read pointer generator which generates a first read pointer in response to a pop-out request of the first consumer;
a second read pointer generator which generates a second read pointer in response to a pop-out request of the second consumer;
a status generator which decides a status of the memory in response to the write pointer and the first and second read pointers; and
a flag generator which transfers a flag to at least one of the data producer and the first and second consumers in response to a status of a multi-port memory output from the status generator.

10. An application processor comprising:
a data producer;
a FIFO buffer which sequentially stores data provided from the data producer;
a plurality of main consumers each of which pops out data stored at the FIFO buffer; and
a plurality of sub consumers each of which pops out data stored at the FIFO buffer and allows a pop-out delay,
wherein the FIFO buffer requests a pop-out operation on at least one of the sub consumers before data to be output to at least one of the main consumers is exhausted, wherein if the difference between a write pointer and at least one of read pointers each corresponding to the main consumers is more than the first threshold value and less than a second threshold value, the FIFO buffer provides at least one of the sub consumers with a flag signal requesting a pop-out operation.

11. The application processor of claim 10 , wherein if the difference between a write pointer and at least one of read pointers each corresponding to the main consumers is less than a first threshold value, the FIFO buffer overwrites data pushed from the data producer at a data area not popped out by the sub consumers.

12. The application processor of claim 11 , wherein the FIFO buffer informs at least one of the sub consumers that the overwritten data is invalid data.

13. The application processor of claim 11 , wherein the FIFO buffer comprises:
a memory which writes data provided from the data producer at a write pointer and outputs according to read pointers each read pointer corresponding to main and sub consumers; and
FIFO control logic which determines a data status of the FIFO buffer referring to the write pointer and the read pointers.

14. The application processor of claim 13 , wherein the FIFO control logic comprises:
a register which stores the first threshold value or the second threshold value;
a plurality of first comparators which compare differences of the write pointer and read pointers each corresponding to the main consumers with the first threshold value or the second threshold value and determine statuses of the FIFO buffer on the main consumers;
a plurality of second comparators which compare differences of the write pointer and read pointers each corresponding to the sub consumers with the first threshold value or the second threshold value and determine statuses of the FIFO buffer on the sub consumers; and
a sub consumer hurry generator which outputs a hurry flag directing data consumption to at least one of the sub consumers when at least one of the sub consumers is determined to be at a full status based on outputs of the first and second comparators and the difference between the write point and a read pointer corresponding to at least one of the main consumers is less than the second threshold value.

15. The application processor of claim 14 , wherein the FIFO control logic comprises:
a producer hurry generator which requests data to be overwritten at a data area not popped out by the at least one sub consumer at the data producer when at least one of the sub consumers is determined to be at a full status based on outputs of the first and second comparators and the difference between the write point and a read pointer corresponding to at least one of the main consumers is less than the first threshold value.

16. The application processor of claim 15 , wherein the FIFO control logic further comprises:
a dirty handler which informs the at least one sub consumer that the overwritten data is invalid.

17. A mobile device comprising:
a hardware codec which generates image data;
a FIFO buffer which has a circular buffer architecture and stores the image data at a memory location corresponding to a write p

Assignees

• Lee Donghan
• Kong Jaesop
• Chun Keemoon
• Samsung Electronics Co Ltd

Inventors

• Lee Donghan
• Kong Jaesop
• Chun Keemoon

Classifications

• G06F5/12 Primary

  Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations · CPC title

• G06F2205/062

  Allowing rewriting or rereading data to or from the buffer · CPC title

• G06F2205/126

  Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag · CPC title

• G06F1/00 Primary

  Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 (architectures of general purpose stored program computers G06F15/76) · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title