Optoelectric device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9537044-B2
Application number	US-201314438188-A
Country	US
Kind code	B2
Filing date	Oct 23, 2013
Priority date	Oct 26, 2012
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A method for manufacturing an optoelectric device comprising a semiconductor substrate, pads on a surface of the substrate; semiconductor elements, each element being in contact with a pad; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair, the method successively comprising the forming of the pads and the forming of the region, wherein the region is formed by nitriding of the substrate, the method comprising the successive steps of: depositing a layer on the substrate; forming portions on the layer; etching the parts of the layer which are not covered with the portions to form the pads; removing the portions; and nitriding the pads and the parts of the substrate which are not covered with the pads, wherein the nitriding step successively comprises: a first step of nitriding of the pads at a first temperature; and a second step of nitriding of the parts of the substrate which are not covered with the pads at a second temperature different from the first temperature.

First claim

What is claimed is:

1. A method for manufacturing an optoelectric device comprising:
a semiconductor substrate;
pads on a surface of the substrate;
semiconductor elements, each element being in contact with a pad; and
a dielectric region extending in the substrate from said surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair,
the method successively comprising the forming of the pads and the forming of the region, wherein the region is formed by nitriding of the substrate, the method comprising the successive steps of:
depositing a layer on the substrate;
forming portions on the layer;
etching the parts of the layer which are not covered with the portions to form the pads;
removing the portions; and
nitriding the pads and the parts of the substrate which are not covered with the pads, wherein the nitriding step successively comprises:
a first step of nitriding of the pads at a first temperature; and
a second step of nitriding of the parts of the substrate which are not covered with the pads at a second temperature different from the first temperature.

2. The method of claim 1 , wherein the second temperature is strictly greater than the first temperature.

3. The method of claim 1 , wherein the second temperature is strictly lower than the first temperature.

4. The method of claim 1 , wherein the substrate comprises a first semiconductor material selected from the group comprising silicon, germanium, silicon carbide, a III-V compound, a II-VI compound, and a combination of these compounds.

5. The method of claim 4 , wherein the first semiconductor material is silicon.

6. The method of claim 4 , wherein each element comprises at least one portion mainly comprising a second semiconductor material in contact with one of the pads, the second semiconductor material being selected from the group comprising silicon, germanium, silicon carbide, a III-V compound, a II-VI compound, and a combination of these compounds.

7. The method of claim 6 , wherein the second semiconductor material is a III-V compound.

8. The method of claim 6 , wherein the second semiconductor material is a III-V compound based on a first group-III element and on a second group-V element and wherein each pad comprises a material promoting the growth of the compound according to the polarity of the second element selected form the group comprising aluminum nitride (AlN), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB 2 ), zirconium nitride (ZrN), silicon carbide (SiC), tantalum carbonitride (TaCN), magnesium nitride (Mg x N y ), magnesium gallium nitride (MgGaN), tungsten (W), tungsten nitride (WN), platinum (Pt), platinum nitride (PtN), and a combination thereof.

9. The method of claim 6 , wherein the second semiconductor material is a III-N compound.

10. The method of claim 1 , wherein said region is made of a nitride of the semiconductor material forming the substrate.

11. The method of claim 1 , wherein the thickness of each pad ranges between 1 nm and 100 nm.

12. The method of claim 1 , wherein the depth of the region ranges between 5 nm and 100 nm.

13. The method of claim 1 , wherein the substrate corresponds to a semiconductor layer covering a support.

14. The method of claim 13 , wherein the support is made of metal.

15. The method of claim 13 , wherein the support is made of glass.

16. The method of claim 1 , wherein the semiconductor substrate is in contact with each pad.

17. The method of claim 1 , wherein at least one of the elements is a microwire or a nanowire.

18. The method of claim 1 , wherein at least one of the elements is pyramid-shaped.

Assignees

• Aledia
• Commissariat Energie Atomique
• Commissariat A L'Energie Atomique Et Aux Energies

Inventors

• Gilet Philippe
• Hugon Xavier
• Vaufrey David
• Bono Hubert
• Hyot Bérangère

Classifications

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y20/00

  Nanooptics, e.g. quantum optics or photonic crystals · CPC title

• H01L33/08

  Electricity · mapped topic

• H01L33/0054

  Electricity · mapped topic

• H01L33/007 Primary

  Electricity · mapped topic