Semiconductor devices including contact patterns having a rising portion and a recessed portion

Patent metadata

Field	Value
Publication number	US-9536968-B2
Application number	US-201514715643-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	Oct 29, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Semiconductor devices may include a gate pattern and a contact pattern disposed on an active region. The contact pattern may include a recessed portion near the gate pattern, and a rising portion away from the gate pattern. The gate pattern may include a gate insulating layer and a gate electrode disposed on the gate insulating layer. An upper surface of the recessed portion may be lower than an upper surface of the rising portion.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate pattern and a contact pattern disposed on an active region,
wherein the gate pattern comprises a gate insulating layer and a gate electrode,
wherein the contact pattern comprises a recessed portion near the gate pattern and a rising portion away from the gate pattern, and
wherein an upper surface of the recessed portion is lower than an upper surface of the rising portion.

2. The semiconductor device of claim 1 , wherein the gate pattern further comprises a surface insulating pattern disposed between the active region and the gate insulating layer,
the surface insulating pattern includes oxidized silicon,
the gate insulating layer includes a metal oxide, and
the gate insulating layer has a U-shaped cross-section to surround side surfaces of the gate electrode.

3. The semiconductor device of claim 1 , further comprising an insulating pattern on the recessed portion of the contact pattern.

4. The semiconductor device of claim 3 , wherein the insulating pattern comprises:
an insulating blocking layer conformally formed on a surface of the active region exposed in an insulating hole and inner walls of the insulating holes; and
an insulating filling layer filling the insulating hole on the insulating blocking layer.

5. The semiconductor device of claim 1 , further comprising a conductive via pattern on the rising portion of the contact pattern.

6. The semiconductor device of claim 1 , further comprising source/drain regions protruding from the active region,
wherein the source/drain regions include one of a SiGe layer and a Si layer, which is epitaxially grown, and
wherein the contact pattern comprises:
a silicide layer contacting the source/drain regions;
a contact barrier layer on the silicide layer; and
a contact plug pattern on the contact barrier layer.

7. The semiconductor device of claim 6 , wherein the source/drain regions are on a plurality of bar shapes to be connected to each other in a form of a bridge.

8. The semiconductor device of claim 6 , further comprising:
an isolation region defining the active region; and
an air gap between the source/drain regions and the active region and isolation region.

9. The semiconductor device of claim 1 , wherein the contact pattern includes a first contact pattern and a second contact pattern disposed in both sides of the gate pattern to have mirrored shapes.

10. The semiconductor device of claim 1 , wherein the upper surface of the recessed portion is lower than an upper surface of the gate electrode, and the upper surface of the rising portion is at an equal level to or higher than the upper surface of the gate electrode.

11. A semiconductor device, comprising:
a gate pattern disposed on an active region, the gate pattern comprising a gate electrode;
a contact pattern disposed adjacent to the gate pattern on the active region; and
an insulating pattern and a via pattern on the contact pattern,
wherein the contact pattern comprises:
a rising portion having an upper surface disposed at an equal level to or higher than an upper surface of the gate electrode; and
a recessed portion having an upper surface lower than the upper surface of the rising portion,
wherein the insulating pattern is on the recessed portion, and
wherein the via pattern is on the rising portion.

12. The semiconductor device of claim 11 , wherein the gate pattern comprises:
a gate insulating layer directly on the active region;
a gate barrier layer on the gate insulating layer; and
the gate electrode on the gate barrier layer,
wherein the gate barrier layer surrounds side surfaces of the gate electrode, and
wherein the gate insulating layer surrounds outer side surfaces of the gate barrier layer.

13. The semiconductor device of claim 11 , wherein the insulating pattern comprises:
an insulating blocking layer conformally formed on the upper surface of the recessed portion and side surfaces of the rising portion; and
an insulating filling layer on the insulating blocking layer,
wherein an upper end portion of the blocking layer is coplanar with an upper end portion of the insulating filling layer.

14. The semiconductor device of claim 11 , further comprising an interlayer insulating layer disposed on the contact pattern and the insulating pattern,
wherein the via pattern comprises:
a via hole vertically passing through the interlayer insulating layer to expose the upper surface of the rising portion of the contact pattern;
a conductive via barrier layer conformally formed on the upper surface of the rising portion exposed in the via hole and inner walls of the via hole; and
a conductive via plug filling the via hole on the conductive via barrier layer.

15. The semiconductor device of claim 11 , wherein the contact pattern comprises:
a silicide layer on the active region;
a contact barrier layer on the silicide layer; and
a contact plug on the contact barrier layer.

16. A semiconductor device, comprising:
isolation regions defining a plurality of parallel active regions, wherein the isolation regions includes trenches recessed such that the active regions have protruding shapes, and trench insulators partially filling the trenches to expose side surfaces of the active regions;
a gate pattern on the active regions, wherein the gate pattern includes a gate insulating layer that is directly on upper surfaces and the exposed side surfaces of the active regions and a gate electrode;
source/drain regions disposed on the active regions;
a contact pattern disposed on the source/drain regions, wherein the contact pattern includes a silicide layer directly on the source/drain regions, a contact barrier layer disposed on the silicide layer, and a contact plug disposed on the contact barrier layer, and the contact pattern comprises a rising portion having an upper surface higher than an upper surface of the gate electrode, and a recessed portion having an upper surface lower than the upper surface of the rising portion; and
a via pattern disposed on the rising portion of the contact pattern.

17. The semiconductor device of claim 16 , further comprising:
an insulating blocking layer conformally formed on the upper surface of the recessed portion and side surfaces of the rising portion; and
an insulating pattern including an insulating filling layer disposed on the blocking layer.

18. The semiconductor device of claim 16 , wherein the source/drain regions are laterally connected in a form of a bridge.

19. The semiconductor device of claim 18 , further comprising air gaps between the source/drain regions and the trench insulators.

20. The semiconductor device of claim 16 , wherein the contact pattern has an L-shaped cross-section viewed in a first direction and an 1 -shaped cross-section viewed in a second direction, or wherein the contact pattern has 1 -shaped cross-sections viewed in the both first and second directions.

Assignees

• Park Sungil
• Kim Munhyeon
• Kim Woonggi
• Cho Keunhwi
• Jun Hwichan
• Kim Dongwon
• Ha Daewon
• Samsung Electronics Co Ltd

Inventors

• Park Sungil
• Kim Munhyeon
• Kim Woonggi
• Cho Keunhwi
• Jun Hwichan
• Kim Dongwon
• Ha Daewon

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075 Primary

  of multilayered thin functional dielectric layers · CPC title