Recessed ohmic contacts in a III-N device

Patent metadata

Field	Value
Publication number	US-9536967-B2
Application number	US-201414572670-A
Country	US
Kind code	B2
Filing date	Dec 16, 2014
Priority date	Dec 16, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.

First claim

What is claimed is:

1. A device comprising:
a III-N layer having an upper side and a lower side, the lower side being opposite the upper side; and
a conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer, the conductive contact comprising:
a first side surface and a second side surface opposite the first side surface;
a top side facing away from the lower side of the III-N layer and extending from the first side surface to the second side surface; and
a bottom side, which is non-planar, facing towards the lower side of the III-N layer, the bottom side comprising:
a first end and a second end opposite the first end;
a first side rising monotonically from the first end to an intermediate point; and
a second side falling monotonically from the intermediate point to the second end; wherein

a separation between the intermediate point and the lower side of the III-N layer is less than a separation between the upper and lower sides of the III-N layer;
the first side surface falls monotonically from the top side to the first end of the bottom side; and
the second side surface falls monotonically from the top side to the second end of the bottom side.

2. The device of claim 1 , the III-N layer comprising a III-N channel layer and a III-N barrier layer, wherein a compositional difference between the III-N channel layer and the III-N barrier layer causes a 2DEG channel to be induced in the III-N channel layer adjacent to the III-N barrier layer.

3. The device of claim 1 , wherein the first side curves from the first end to the intermediate point and the second side curves from the second end to the intermediate point, forming a substantially rounded trench shape in the bottom side of the conductive contact.

4. The device of claim 1 , the III-N layer comprising:
a GaN layer;
a III-N spacer layer on the GaN layer; and
a III-N barrier layer on the III-N spacer layer.

5. The device of claim 4 , wherein the III-N spacer layer has a larger bandgap than the III-N barrier layer.

6. The device of claim 5 , wherein:
the first end or the second end or both extend to the III-N spacer layer; and
the intermediate point is located in the III-N barrier layer.

7. The device of claim 6 , wherein at least one of the first end and the second end extends through the III-N spacer layer to contact the GaN layer.

8. The device of claim 4 , wherein the III-N spacer layer comprises AlN and the III-N barrier layer comprises AlGaN.

9. The device of claim 1 , wherein the conductive contact is a source contact, the device further comprising a drain contact and a gate contact, forming a transistor.

10. The device of claim 9 , wherein the drain contact comprises:
a drain top side facing away from the lower side of the III-N layer; and
a drain bottom side facing towards the lower side of the III-N layer, the bottom side comprising:
a drain first end and a drain second end opposite the drain first end;
a drain first side rising from the drain first end to a drain intermediate point closer to the top side than the drain first end; and
a drain second side falling from the drain intermediate point to a drain second end further from the top side than the drain intermediate point.

11. The device of claim 10 , wherein the transistor is a lateral transistor having the drain, source, and gate on a same side.

12. The device of claim 10 , wherein the drain first side rises monotonically from the drain first end to the drain intermediate point and the drain second bottom side falls monotonically from the drain intermediate point to the drain second end.

13. The device of claim 1 , wherein the conductive contact has a normalized contact resistance of 0.3 Ohm-mm or less.

14. The device of claim 1 , wherein the first end or the second end has a width less than 300 nanometers.

15. The device of claim 1 , wherein the III-N layer is on a substrate.

16. A method for fabricating a device, the method comprising:
forming a III-N layer having an upper side and a lower side, the lower side being opposite the upper side;
forming a recess in a surface on the upper side of the III-N layer, including etching the surface of the III-N layer using a resist pattern;
forming a conductive contact over the recess in the surface of the III-N layer, the conductive contact comprising:
a first side surface and a second side surface opposite the first side surface;
a top side facing away from the lower side of the III-N layer and extending from the first side surface to the second side surface; and
a bottom side, which is non-planar, facing towards the lower side of the III-N layer, the bottom side comprising:
a first end and a second end opposite the first end;
a first side rising monotonically from the first end to an intermediate point; and
a second side falling monotonically from the intermediate point to the second end; wherein

a separation between the intermediate point and the lower side of the III-N layer is less than a separation between the upper and lower sides of the III-N layer;
the first side surface falls monotonically from the top side to the first end of the bottom side; and
the second side surface falls monotonically from the top side to the second end of the bottom side.

17. The method of claim 16 , comprising heating the device to a temperature between 300° C. and 600° C.

18. The method of claim 17 , wherein heating the device comprises heating the device for one to three minutes.

19. The method of claim 16 , wherein etching the surface of the III-N layer comprises performing a dry etch using a chlorine based gas.

20. The method of claim 19 , wherein etching the surface of the III-N layer comprises performing a plasma etch in Cl 2 plasma at an RF bias of 25 W or less.

21. The method of claim 16 , wherein forming the III-N layer comprises forming:
a GaN layer;
an AlN spacer layer on the GaN layer; and
an AlGaN layer on the AlN spacer layer.

22. The method of claim 21 , wherein forming the recess comprises forming the recess through the AlGaN layer up to the AlN spacer layer.

23. The method of claim 21 , wherein forming the recess comprises forming the recess through the AlGaN layer and into the AlN spacer layer.

24. The method of claim 21 , wherein forming the recess comprises forming the recess through the AlGaN layer and the AlN spacer layer and into the GaN layer.

Assignees

• Transphorm Inc

Inventors

• Kikkawa Toshihide
• Kiuchi Kenji
• Hosoda Tsutomu
• Kanamura Masahito
• Mochizuki Akitoshi

Classifications

• H10D64/0125

  characterised by the sectional shape, e.g. T or inverted T · CPC title

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10D64/0116 Primary

  to Group III-V semiconductors · CPC title