Field-isolated bulk FinFET

Patent metadata

Field	Value
Publication number	US-9536882-B2
Application number	US-201414574504-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a fin structure on said semiconductor substrate, said fin structure being perpendicular to said semiconductor substrate and comprising an upper portion and a lower portion;
a source region and a drain region adjacent to said fin structure;
a gate structure surrounding said upper portion of said fin structure;
a well region below said fin structure; and
a well contact point in said semiconductor substrate,
said lower portion of said fin structure comprising a sub-fin, said sub-fin being between the region surrounded by said gate structure and said semiconductor substrate, said sub-fin directly contacting said semiconductor substrate, said sub-fin comprising an upper portion of said sub-fin and a lower portion of said sub-fin,
said upper portion of said fin structure and said upper portion of said sub-fin being undoped, and
an electrical potential applied from said well contact point to said lower portion of said sub-fin through said well region reducing leakage currents from said upper portion of said fin structure.

2. The semiconductor device according to claim 1 , wherein said lower portion of said sub-fin is doped.

3. The semiconductor device according to claim 1 , said semiconductor substrate further comprising:
a bulk silicon wafer having a top surface and a bottom surface; and
a conductive layer formed on said top surface of said bulk silicon wafer.

4. The semiconductor device according to claim 3 , said semiconductor substrate further comprising:
an undoped silicon layer formed on a top surface of said conductive layer relative to said bulk silicon wafer.

5. The semiconductor device according to claim 3 , said conductive layer further comprising said well contact point.

6. The semiconductor device according to claim 3 , said conductive layer comprising said well region.

7. The semiconductor device according to claim 6 , said fin structure being above said well region relative to said semiconductor substrate.

8. The semiconductor device according to claim 3 , further comprising:
an oxide layer on said conductive layer, said conductive layer being between said bulk silicon wafer and said oxide layer.

9. The semiconductor device according to claim 1 , said source region, said drain region, and said gate structure defining a fin field effect transistor (FinFET).

10. A semiconductor device comprising:
a bulk silicon wafer having a top surface and a bottom surface;
a conductive layer formed on said top surface of said bulk silicon wafer, said conductive layer having a well contact point;
an oxide layer on said conductive layer, said conductive layer being between said bulk silicon wafer and said oxide layer, said conductive layer comprising a well region;
a fin structure extending through said oxide layer, said fin structure comprising an upper portion and a lower portion, said upper portion of said fin structure being undoped;
a source region and a drain region adjacent to said fin structure; and
a gate structure surrounding said upper portion of said fin structure, said source and drain regions and said gate structure defining a fin field effect transistor (FinFET),
said lower portion of said fin structure comprising a sub-fin between the region surrounded by said gate structure and said bulk silicon wafer, said sub-fin comprising an upper portion and a lower portion, said upper portion of said sub-fin being undoped, said lower portion of said sub-fin being doped,
a portion of said well region of said conductive layer comprising part of said lower portion of said sub-fin, and
an electrical potential applied from said well contact point to said lower portion of said sub-fin through said well region reducing leakage currents from said upper portion of said fin structure.

11. The semiconductor device according to claim 10 , further comprising:
n-type versions of said fin structure; and
p-type versions of said fin structure,
said n-type versions of said fin structure and said p-type versions of said fin structure having complementary doping and electrical potentials.

12. The semiconductor device according to claim 11 , further comprising:
said n-type versions of said fin structure and said p-type versions of said fin structure having complementary doping and electrical potentials creating complementary metal-oxide-semiconductor (CMOS) structures.

13. The semiconductor device according to claim 10 , further comprising:
a first common p-well well interconnecting a first set of sub-fins of n-type structures; and
a second common n-well well interconnecting a second set of sub-fins of p-type structures.

Assignees

• Globalfoundries Inc

Inventors

• Anderson Brent A
• Nowak Edward J
• Robison Robert R
• Scholze Andreas

Classifications

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P50/264

  by chemical means · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title