Bond pad structure for low temperature flip chip bonding

Patent metadata

Field	Value
Publication number	US-9536848-B2
Application number	US-201414515969-A
Country	US
Kind code	B2
Filing date	Oct 16, 2014
Priority date	Oct 16, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

First claim

What is claimed is:

1. A method comprising:
forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and
bonding the first and second semiconductor devices together through the first and second bond pads,
wherein the metal segments of the first bond pad on the first semiconductor device comprise only columns of segments, the columns being staggered with respect to each other, and the metal segments of the second bond pad on the second semiconductor device comprise only rows of segments, the rows being staggered with respect to each other, wherein the columns of segments are perpendicular to the rows of segments.

2. The method according to claim 1 , comprising forming a larger first bond pad on the first semiconductor device than the second bond pad on the second semiconductor device.

3. The method according to claim 1 , comprising patterning the first and second bond pads on the first and second semiconductor devices, respectively, by a copper damascene process.

4. The method according to claim 1 , further comprising surrounding the first and second bond pads on the first and second semiconductor devices, respectively, by a dielectric layer; and
bonding the first and second semiconductor devices together through the dielectric layers in a chemical or plasma activated fusion bonding process.

5. The method according to claim 1 , wherein the first and second semiconductor devices include a low temperature inorganic layer around the metal segments, the method further comprising planarizing the first and second bond pads and the low temperature inorganic layer on the first and second semiconductor devices, respectively, by Chemical Machine Polishing (CMP) before bonding together.

6. The method according to claim 1 , further comprising patterning the bond pads on the first and second semiconductor devices by a copper damascene process, and bonding the first and second semiconductor devices together through copper-to-copper bonds in the patterned bond pads.

Assignees

• Globalfoundries Inc

Inventors

• England Luke
• Klewer Christian

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/016

  Cleaning · CPC title