Method of making integrated circuit

Patent metadata

Field	Value
Publication number	US-9536781-B2
Application number	US-201514831163-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Sep 23, 2011
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

First claim

What is claimed is:

1. A method of fabricating a circuit, said method comprising:
providing a die, said die having a side;
applying an encapsulant in an uncured state to said die, except for said side;
affixing a conductive stud directly on said die which extends from said side;
affixing a first dielectric layer in an uncured state to said side of said die, when the encapsulant is in the uncured state, said first dielectric layer having a first side and a second side, wherein said first side of said first dielectric layer is affixed to said side of said die, said conductive stud piercing said first side of said first dielectric layer;
forming a first via through said first dielectric layer between said conductive stud and said second side, wherein said first via is electrically connected to said conductive stud; and
curing said uncured encapsulant and said first dielectric layer in the uncured state.

2. The method of claim 1 , wherein curing said uncured encapsulant and said first dielectric layer in the uncured state comprises:
curing said uncured encapsulant and said first dielectric layer in the uncured state, simultaneously.

3. The method of claim 1 , and further comprising locating said die proximate a heat spreader.

4. The method of claim 1 , and further comprising affixing a conductive layer to said second side, said conductive layer electrically connected to said first via.

5. The method of claim 4 and further comprising:
affixing a second dielectric layer to said conductive layer, said second dielectric layer having a first side and a second side, wherein said first side of said second dielectric layer is located adjacent said conductive layer; and
forming a second via between said conductive layer and said second side of said second dielectric layer.

6. The method of claim 5 and further comprising affixing a connection mechanism to said second side of said second dielectric layer, said connection mechanism being electrically connected to said second via.

7. The method of claim 1 , wherein said affixing the first dielectric layer comprises affixing a first dielectric material to a carrier and applying said dielectric material with said carrier to said side of said die.

8. The method of claim 7 and further comprising removing said carrier.

9. A method of fabricating a circuit, said method comprising:
providing a die, said die having a side, wherein a conductive stud extends from said side in a direction that is substantially normal to said side;
affixing a first dielectric layer to said side of said die, said first dielectric layer having a first side and a second side, wherein said first side of said first dielectric layer is affixed to said side of said die;
piercing said first side of said first dielectric layer with said conductive stud;
forming a first via through said first dielectric layer between said conductive stud and said second side, wherein said first via is electrically connected to said conductive stud;
applying an uncured encapsulant to said die; and
curing said encapsulant and said first dielectric layer simultaneously.

10. The method of claim 9 , wherein said first dielectric layer has a conductive layer affixed to said second side and further comprising electrically connecting said conductive layer to said first via.

11. The method of claim 10 and further comprising:
affixing a second dielectric layer to said conductive layer, said second dielectric layer having a first side and a second side, wherein said first side of said second dielectric layer is located adjacent said conductive layer; and
forming a second via between said conductive layer and said second side of said second dielectric layer.

12. The method of claim 11 and further comprising affixing a connection mechanism to said second side of said second dielectric layer, said connection mechanism being electrically connected to said second via.

Assignees

• Texas Instruments Inc

Inventors

• Gallegos Bernardo
• Castro Abram

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/01936

  in solid form, e.g. by using a powder or by laminating a foil · CPC title