Multi-layered chip electronic component

Patent metadata

Field	Value
Publication number	US-9536647-B2
Application number	US-201213715899-A
Country	US
Kind code	B2
Filing date	Dec 14, 2012
Priority date	Aug 28, 2012
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

There is provided a multi-layered chip electronic component including: a multi-layered body formed by stacking a plurality of magnetic layers; and conductive patterns disposed between the plurality of magnetic layers and electrically connected in a lamination direction to form coil patterns, wherein in a case in which a single coil pattern in the coil pattern is projected in the length and width directions of the multi-layered body, when an area of the magnetic layer inside of the coil pattern is defined as Ai and an area of the magnetic layer outside of the coil pattern is defined as Ao, 0.40≦Ai:Ao≦1.03 is satisfied.

First claim

What is claimed is:

1. A multi-layered chip electronic component, comprising:
a multi-layered body including a plurality of magnetic layers on which conductive patterns are formed and via electrodes electrically connecting the conductive patterns to form coil patterns in a lamination direction, the plurality of magnetic layers including first magnetic layers forming a common layer with the conductive patterns and second magnetic layers interposed between the first magnetic layers, wherein:
the coil pattern is projected in the length and width directions of the multi-layered body,
an area formed in the inside of the coil pattern is defined as Ai and an area formed outside of the coil pattern is defined as Ao, 0.57≦Ai:Ao≦1.03 being satisfied, and
an area of the coil pattern is defined as Ae and the overall area of the multi-layered body in the length and width directions is defined as At, 0.13≦Ae:At≦0.78 being satisfied.

2. The multi-layered chip electronic component of claim 1 , wherein the first magnetic layer is printed to have a thickness equal to that of the conductive pattern that is printed on the second magnetic layer.

3. The multi-layered chip electronic component of claim 1 , wherein a length and a width of the multi-layered chip electronic component have a range of 2.0±0.1 mm and 1.6±0.1 mm, respectively.

4. The multi-layered chip electronic component of claim 1 , wherein the Ai is an area of the magnetic layer occupying an inside of the coil pattern.

5. The multi-layered chip electronic component of claim 1 , wherein the Ao is an area of the magnetic layer occupying an outside of the coil pattern.

6. The multi-layered chip electronic component of claim 1 , wherein the coil pattern includes the conductive pattern in the width direction and the conductive pattern in the length direction, and a width of a margin part formed in the width direction with respect to the conductive pattern in the length direction is narrower than a width of a margin part formed in the length direction with respect to the conductive pattern in the width direction.

7. A multi-layered chip electronic component, comprising:
a multi-layered body formed by stacking a plurality of magnetic layers; and
conductive patterns disposed between the plurality of magnetic layers and electrically connected in a lamination direction to form coil patterns, the plurality of magnetic layers including first magnetic layers forming a common layer with the conductive patterns and second magnetic layers interposed between the first magnetic layers, wherein:
a single coil pattern in the coil pattern is projected in the length and width directions of the multi-layered body, and
an area of the magnetic layer inside of the coil pattern is defined as Ai, and an area of the magnetic layer outside of the coil pattern is defined as Ao, 0.57≦Ai:Ao≦1.03 being satisfied.

8. The multi-layered chip electronic component of claim 7 , wherein an area of the coil pattern is defined as Ae and an overall area of the multi-layered body projected in the length and width direction is defined as At, 0.13≦Ae:At≦0.78 being satisfied.

9. The multi-layered chip electronic component of claim 7 , wherein the magnetic layer includes:
a second magnetic layer including a fired magnetic green sheet; and
a first magnetic layer fired while having a magnetic substance applied thereto to have a thickness equal to that of the conductive pattern printed on the second magnetic layer.

10. The multi-layered chip electronic component of claim 7 , wherein the coil pattern includes the conductive pattern in the width direction and the conductive pattern in the length direction, and a width of a margin part formed in the width direction with respect to the conductive pattern in the length direction is narrower than a width of a margin part formed in the length direction with respect to the conductive pattern in the width direction.

11. The multi-layered chip electronic component of claim 7 , wherein a length and a width of the multi-layered chip electronic component have a range of 2.0±0.1 mm and 1.6±0.1 mm, respectively.

12. The multi-layered chip electronic component of claim 7 , wherein a length of the multi-layered body is 2.1 mm or less and a width of the multi-layered body is 1.7 mm or less.

13. The multi-layered chip electronic component of claim 7 , wherein:
the first magnetic layer is printed to have a thickness equal to that of the conductive pattern that is printed on the second magnetic layer, and
the first magnetic layer is printed to have a thickness greater than that of the second magnetic layer.

Assignees

• Samsung Electro Mech

Inventors

• Hahn Jin Woo
• Song So Yeon
• An Sung Yong
• Moon Byeong Cheol
• Son Soo Hwan

Classifications

• H01F27/292

  Surface mounted devices · CPC title

• H01F5/003 Primary

  Printed circuit coils · CPC title

• H01F17/0033

  with the coil helically wound around a magnetic core · CPC title

• H01F17/0013 Primary

  with stacked layers · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title