Pattern failure discovery by leveraging nominal characteristics of alternating failure modes

US9536299B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9536299-B2
Application numberUS-201414542430-A
CountryUS
Kind codeB2
Filing dateNov 14, 2014
Priority dateJan 16, 2014
Publication dateJan 3, 2017
Grant dateJan 3, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Methods and systems for detecting defects on a wafer are provided. One method includes acquiring output for a wafer generated by an inspection system. Different dies are printed on the wafer with different process conditions. The different process conditions correspond to different failure modes for the wafer. The method also includes comparing the output generated for a first of the different dies printed with the different process conditions corresponding to a first of the different failure modes with the output generated for a second of the different dies printed with the different process conditions corresponding to a second of the different failure modes opposite to the first of the different failure modes. In addition, the method includes detecting defects on the wafer based on results of the comparing step.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer-implemented method for detecting defects on a wafer, comprising: acquiring output for a wafer generated by an inspection system, wherein different dies are printed on the wafer with different process conditions, and wherein the different process conditions correspond to different failure modes for the wafer; comparing the output generated for a first of the different dies printed with the different process conditions corresponding to a first of the different failure modes with the output generated for a second of the different dies printed with the different process conditions corresponding to a second of the different failure modes opposite to the first of the different failure modes, wherein the different process conditions corresponding to the different failure modes comprise process conditions at corners of a process window for the wafer, wherein the different process conditions corresponding to the first of the different failure modes are at a first of the corners of the process window, and wherein the different process conditions corresponding to the second of the different failure modes are at a second of the corners of the process window opposite to the first of the corners; detecting defects on the wafer based on results of said comparing the output, wherein said acquiring, said comparing the output, and said detecting are performed by a computer system; and determining he process window by: simulating printing of the wafer to determine an expected process window; acquiring additional output for another wafer generated the inspection system or another inspection system, wherein different dies are printed on the other wafer with additional process conditions, and wherein the additional process conditions comprise process conditions adjacent to expected corners of the expected process window and farther from nominal process conditions than the expected corners; comparing the additional output generated for a first of the different dies printed on the other wafer with the additional process conditions adjacent to a first of the expected corners with the additional output generated for a second of the different dies printed on the other wafer with the additional process conditions adjacent to a second of the expected corners opposite from the first of the expected corners; detecting detects on the other wafer based on results of comparing the additional output; and determining the process window based on the defects detected on the other wafer. 2. The method of claim 1 , wherein the defects that are detected on the wafer comprise systematic defects. 3. The method of claim 1 , wherein at least some locations of the defects that are detected on the wafer comprise previously undetected pattern failures in a design for the wafer. 4. The method of claim 1 , wherein the comparing the output step comprises comparing the output generated for a third of the different dies printed on the wafer with the different process conditions corresponding to a third of the different failure modes with the output generated for a fourth of the different dies printed on the wafer with the different process conditions corresponding to a fourth of the different failure modes opposite to the third of the different failure modes. 5. The method of claim 1 , further comprising binning the defects detected on the wafer into different groups, wherein the binning is performed separately for the different dies that are printed on the wafer with the different process conditions. 6. The method of claim 5 , wherein the different groups correspond to different patterns in a design for the wafer. 7. The method of claim 1 , further comprising selecting one or more of the defects detected on the wafer for defect review, wherein said selecting is performed separately for the different dies that are printed on the wafer at the different process conditions. 8. The method of claim 1 , wherein all dies on the wafer are printed with the process conditions corresponding to one of the different failure modes. 9. The method of claim 1 , wherein two or more of the different dies are printed on the wafer with the different process conditions that are the same. 10. The method of claim 1 , wherein the first and the second of the different dies are printed adjacent to each other on the wafer in a row of dies extending across substantially an entire dimension of the wafer, and wherein the row of dies comprises dies printed with the different process conditions corresponding to the first of the different failure modes alternating with dies printed with the different process conditions corresponding to the second of the different failure modes. 11. The method of claim 1 , wherein no dies on the wafer are printed with nominal process conditions for the process window for the different process conditions. 12. The method of claim 1 , wherein no more than one of all dies on the wafer is printed with nominal process conditions for the process window for the different process conditions. 13. The method of claim 1 , wherein the method does not comprise comparing the output generated for any of the different dies printed on the wafer with output for a die printed on the wafer with nominal process conditions for the process window for the different process conditions. 14. The method of claim 1 , wherein the corners of the process window are defined by maximum and minimum values for the different process conditions, wherein the different process conditions further comprise process conditions at inner corners of the process window, and wherein the inner corners are adjacent to the corners and closer to nominal process conditions than the corners. 15. The method of claim 14 , wherein the comparing the output step comprises comparing the output generated for a third of the different dies printed on the wafer with the different process conditions at a first of the inner corners of the process window with the output generated for a fourth of the different dies printed on the wafer with the different process conditions at a second of the inner corners opposite to the first of the inner corners. 16. The method of claim 1 , wherein the method further comprises determining if the process window is correct based on the defects detected on the wafer. 17. A non-transitory computer-readable medium, storing program instructions executable on a computer system for performing a computer-implemented method for detecting defects on a wafer, wherein the computer-implemented method comprises: acquiring output for a wafer generated by an inspection system, wherein different dies are printed on the wafer with different process conditions, and wherein the different process conditions correspond to different failure modes for the wafer; comparing the output generated for a first of the different dies printed with the different process conditions corresponding to a first of the different failure modes with the output generated for a second of the different dies printed with the different process conditions corresponding to a second of the different failure modes opposite to the first of the different failure modes, wherein the different process conditions corresponding to the different failure modes comprise process conditions at corners of a process window for the wafer, wherein the different process conditions corresponding to the first of the different failure modes are at a first of the corners of the process window, and wherein the different process conditions corresponding to the second of the different failure modes are at a seco

Assignees

Inventors

Classifications

  • Monitoring of warpages, curvatures, damages, defects or the like · CPC title

  • G06T7/001Primary

    using an image reference approach · CPC title

  • Electricity · mapped topic

  • Semiconductor; IC; Wafer · CPC title

  • characterised by multiple measurements, corrections, marking or sorting processes · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9536299B2 cover?
Methods and systems for detecting defects on a wafer are provided. One method includes acquiring output for a wafer generated by an inspection system. Different dies are printed on the wafer with different process conditions. The different process conditions correspond to different failure modes for the wafer. The method also includes comparing the output generated for a first of the different …
Who is the assignee on this patent?
Kla Tencor Corp, Kla Tencor Corp
What technology area does this patent fall under?
Primary CPC classification G06T7/001. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).