Non-volatile memory interface

Patent metadata

Field	Value
Publication number	US-9535829-B2
Application number	US-201314128669-A
Country	US
Kind code	B2
Filing date	Jul 26, 2013
Priority date	Jul 26, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

First claim

What is claimed is:

1. A method comprising:
sending an indication that a request is being sent, the indication being sent to a non-volatile memory via a bus between a memory interface and the non-volatile memory;
sending a preamble to the non-volatile memory via the bus, the preamble for use by the non-volatile memory to prepare to acquire the request from the bus;
sending the request to the non-volatile memory via the bus, the request including an address for identifying a location in the non-volatile memory containing data to be read;
acquiring an indication via the bus that the non-volatile memory is ready to send information;
sending an indication via the bus that access to the bus has been granted to the non-volatile memory; and
acquiring the information from the non-volatile memory via the bus, the information including the data.

2. The method of claim 1 , wherein the request includes a command that indicates that a read operation is to be performed by the non-volatile memory.

3. The method of claim 1 , further comprising:
sending an indication via the bus that the memory interface has a request to send.

4. The method of claim 1 , further comprising:
acquiring a strobe signal from the bus; and
acquiring the information from the bus using the acquired strobe signal.

5. The method of claim 1 , wherein the bus includes a plurality of wires and, wherein the request is sent to the non-volatile memory and the information is acquired from the non-volatile memory on the same wire of the plurality of wires.

6. The method of claim 1 , further comprising:
sending an indication via the bus that indicates the non-volatile memory has ownership of the bus.

7. The method of claim 1 , further comprising:
acquiring an indication from the bus that the non-volatile memory is no longer sending the information on the bus.

8. The method of claim 7 , wherein the indication that the non-volatile memory is no longer sending the information on the bus includes a post-amble.

9. The method of claim 7 , wherein the bus includes a plurality of wires and wherein the information sent by the non-volatile memory is acquired on a first wire of the plurality of wires and the indication that the non-volatile memory is no longer sending the information is acquired on a second wire of the plurality of wires.

10. A method comprising:
sending an indication that a request is being sent, the indication being sent to a non-volatile memory via a bus between a memory interface and the non-volatile memory;
sending a preamble to the non-volatile memory via the bus, the preamble for use by the non-volatile memory to prepare to acquire the request from the bus;
sending the request to the non-volatile memory via the bus, the request including an address for use in identifying a location in non-volatile memory to be written;
sending data to be written to the non-volatile memory via the bus;
acquiring an indication that the non-volatile memory has a response to send to the memory interface via the bus;
granting access to the bus to the non-volatile memory, the access being granted via the bus; and
acquiring a response from the non-volatile memory via the bus, the response including a status associated with the request.

11. The method of claim 10 , wherein the bus includes a plurality of wires, and wherein the request is acquired and the data is sent on the same wire of the plurality of wires.

12. An apparatus comprising:
an interface to a non-volatile memory; and
processing logic to:
send an indication that a request is being sent, the indication being sent to a non-volatile memory via a bus,
send a preamble to the non-volatile memory via the bus, the preamble for use by the non-volatile memory to prepare to acquire the request from the bus,
send the request to the non-volatile memory via the bus, the request including an address for identifying a location in the non-volatile memory containing data to be read,
acquire an indication via the bus that the non-volatile memory is ready to send information,
send an indication via the bus that access to the bus has been granted to the non-volatile memory,
send the information from the non-volatile memory via the bus, the information including the data.

13. The apparatus of claim 12 , wherein the request includes a command that indicates that a read operation is to be performed by the non-volatile memory.

14. The apparatus of claim 12 , wherein the processor logic is further configured to:
acquire a strobe signal from the bus; and
acquire the information from the bus using the acquired strobe signal.

15. The apparatus of claim 12 , wherein the bus includes a plurality of wires and, wherein that read request is sent and the information from the non-volatile memory is acquired on the same wire of the plurality of wires.

16. The apparatus of claim 12 , wherein the processor logic is further configured to:
send an indication via the bus that indicates the non-volatile memory has ownership of the bus.

17. The apparatus of claim 12 , wherein the processor logic is further configured to:
acquire an indication from the bus that the non-volatile memory is no longer sending the information on the bus.

18. The apparatus of claim 17 , wherein the indication that the non-volatile memory is no longer sending the information on the bus includes a post-amble.

19. The apparatus of claim 17 , wherein the bus includes a plurality of wires and wherein the information sent by the non-volatile memory is acquired on a first wire of the plurality of wires and the indication that the non-volatile memory is no longer sending the information is acquired on a second wire of the plurality of wires.

20. The apparatus of claim 12 , further comprising:
the non-volatile memory communicatively coupled to the interface;
a volatile memory communicatively coupled to the processing logic;
a host controller communicatively coupled to a volatile memory interface; and
a bus communicatively coupled to the non-volatile memory interface and the non-volatile memory.

Assignees

• Intel Corp

Inventors

• Ooi Eng Hun
• Royer Jr Robert J
• Williams Michael W
• Wilcox Jeffrey R
• Trivedi Ritesh B
• Fanning Blaise

Classifications

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F13/12

  using hardware independent of the central processor, e.g. channel or peripheral processor · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title