Method and apparatus for continued retirement during commit of a speculative region of code

Patent metadata

Field	Value
Publication number	US-9535744-B2
Application number	US-201313931860-A
Country	US
Kind code	B2
Filing date	Jun 29, 2013
Priority date	Jun 29, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

First claim

What is claimed is:

1. A method implemented in a processor comprising:
identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and
retiring one or more of plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete, wherein the commit operation associated with the first transactional memory region includes at least one speculative execution, wherein the one or more of plurality of operations that follow the first transactional memory region are treated as part of the first transactional memory region so that states of architectural registers of the processor from execution of the first transactional memory region and the one or more of the plurality of operations are preserved.

2. The method as in claim 1 wherein the operations are microoperations (uops).

3. The method as in claim 1 further comprising:
stalling a retirement operation of a current transactional memory region until a previous transactional memory region is ready to commit.

4. The method as in claim 1 further comprising:
detecting an abort operation to abort execution of the plurality of operations following the first transactional memory region; and
restoring the architectural registers to a state existing at a start of the first transactional memory region; and
discarding results from the first transactional memory region and/or the plurality of operations following the first transactional memory region.

5. The method as in claim 4 wherein restoring the architectural registers comprises reading data associated with the state from a copy-on-write (COW) buffer.

6. The method as in claim 1 further comprising:
detecting that retirement of an operation of the plurality of operations following the first transactional memory region would result in the inability to restore the architectural registers to a state existing at a start of the first transactional memory region; and
responsively stalling retirement of the operation.

7. The method as in claim 6 wherein detecting comprises detecting that retirement cannot be undone by restoring the architectural registers from a copy-on-write (COW) buffer.

8. A processor comprising:
first logic to identify a plurality of transactional memory regions in program code, including a first transactional memory region; and
second logic to retire one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete, wherein the commit operation associated with the first transactional memory region includes at least one speculative execution,
and wherein the first logic and second logic treat the plurality of operations that follow the first transactional memory region as part of the first transactional memory region for the purposes of retiring operations so that states of architectural registers of the processor from execution of the first transactional memory region and the one or more of the plurality of operations are preserved.

9. The processor as in claim 8 wherein the operations are microoperations (uops).

10. The processor as in claim 8 wherein the second logic stalls a retirement operation of a current transactional memory region until a previous transactional memory region is ready to commit.

11. The processor as in claim 8 comprising additional logic to:
detect an abort operation to abort execution of the plurality of operations following the first transactional memory region; and
restore the architectural registers to a state existing at a start of the first transactional memory region; and
discard results from the first transactional memory region and/or the plurality of operations following the first transactional memory region.

12. The processor as in claim 11 further comprising:
a copy-on-write (COW) buffer, wherein restoring the architectural registers comprises reading data associated with the state from the COW buffer.

13. The processor as in claim 8 comprising additional logic to:
detect that a retire operation of the plurality of operations following the first transactional memory region would result in the inability to restore the architectural registers to a state existing at a start of the first transactional memory region; and
responsively stall retirement of the operation.

14. The processor as in claim 13 wherein detecting comprises detecting that retirement cannot be undone by restoring the architectural registers from a copy-on-write (COW) buffer.

15. A system comprising:
a memory for storing program code and data;
a input/output communication interface for communicating with one or more peripheral devices;
a network communication interface for communicatively coupling the system to a network; and
a processor comprising:
first logic to identify a plurality of transactional memory regions in program code, including a first transactional memory region; and
second logic to retire one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete, wherein the commit operation associated with the first transactional memory region includes at least one speculative execution,
and wherein the first logic and second logic treat the plurality of operations that follow the first transactional memory region as part of the first transactional memory region for the purposes of retiring operations so that states of architectural registers of the processor from execution of the first transactional memory region and the one or more of the plurality of operations are preserved.

16. The system as in claim 15 wherein the operations are microoperations (uops).

17. The system as in claim 15 wherein the second logic stalls a retirement operation of a current transactional memory region until a previous transactional memory region is ready to commit.

18. The system as in claim 15 wherein the processor comprises additional logic to:
detect an abort operation to abort execution of the plurality of operations following the first transactional memory region; and
restore the architectural registers to a state existing at a start of the first transactional memory region; and
discard results from the first transactional memory region and/or the plurality of operations following the first transactional memory region.

19. The system as in claim 18 wherein the processor further comprises:
a copy-on-write (COW) buffer, wherein restoring the architectural registers comprises reading data associated with the state from the COW buffer.

20. The system as in claim 15 wherein the processor comprises additional logic to:
detect that a retire operation of the plurality of operations following the first transactional memory region would result in the inability to restore the architectural registers to a state existing at a start of the first transactional memory region; and
responsively stall retirement of the operation.

21. The system as in claim 20 wherein detecting comprises detecting that retirement cannot be undone by restoring the architectural registers from a copy-on-write (COW) buffer.

Assignees

• Intel Corp

Inventors

• Rajwar Ravi
• Merten Matthew C
• Wang Christine E
• Kadgi Vijaykumar B
• Parthasarathy Rajesh S

Classifications

• G06F9/3857

  Physics · mapped topic

• G06F9/528

  by using speculative mechanisms · CPC title

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F9/466

  Transaction processing · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title