Providing early instruction execution in an out-of-order (ooo) processor, and related apparatuses, methods, and computer-readable media

Patent metadata

Field	Value
Publication number	US-2016170770-A1
Application number	US-201414568637-A
Country	US
Kind code	A1
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Providing early instruction execution in an out-of-order (OOO) processor, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, an apparatus comprises an early execution engine communicatively coupled to a front-end instruction pipeline and a back-end instruction pipeline of an OOO processor. The early execution engine is configured to receive an incoming instruction from the front-end instruction pipeline, and determine whether an input operand of one or more input operands of the incoming instruction is present in a corresponding entry of one or more entries in an early register cache. The early execution engine is also configured to, responsive to determining that the input operand is present in the corresponding entry, substitute the input operand with a non-speculative immediate value stored in the corresponding entry. In some aspects, the early execution engine may execute the incoming instruction using an early execution unit and update the early register cache.

First claim

What is claimed is:

1 . An apparatus comprising an early execution engine,
the early execution engine communicatively coupled to a front-end instruction pipeline and a back-end instruction pipeline of an out-of-order (OOO) processor; the early execution engine comprising:
an early execution unit; and
an early register cache; and
the early execution engine configured to:
receive an incoming instruction from the front-end instruction pipeline;
determine whether an input operand of one or more input operands of the incoming instruction is present in a corresponding entry of one or more entries in the early register cache; and
responsive to determining that the input operand is present in the corresponding entry, substitute the input operand with a non-speculative immediate value stored in the corresponding entry.

2 . The apparatus of claim 1 , wherein the early execution engine is further configured to, responsive to determining that the input operand is not present in the corresponding entry:
invalidate an entry of the early register cache corresponding to an output operand of the incoming instruction; and provide the incoming instruction as an outgoing instruction to the back-end instruction pipeline for execution.

3 . The apparatus of claim 1 , wherein the early execution engine is further configured to:
determine whether the incoming instruction is an early-execution-eligible instruction; and responsive to determining that the incoming instruction is the early-execution-eligible instruction:
execute the early-execution-eligible instruction using the early execution unit of the early execution engine;
write an output value of the early-execution-eligible instruction to an entry of the early register cache corresponding to an output operand of the early-execution-eligible instruction; and
provide an outgoing instruction to the back-end instruction pipeline for execution.

4 . The apparatus of claim 3 , wherein the early execution engine is further configured to, responsive to determining that the incoming instruction is not the early-execution-eligible instruction:
invalidate the entry of the early register cache corresponding to the output operand of the incoming instruction; and provide the incoming instruction as the outgoing instruction to the back-end instruction pipeline for execution.

5 . The apparatus of claim 1 , wherein the early execution engine is further configured to:
receive one or more architectural register values from the OOO processor, the one or more architectural register values corresponding to the one or more entries in the early register cache; and update the one or more entries of the early register cache to store the one or more architectural register values.

6 . The apparatus of claim 1 , wherein the early execution engine is further configured to:
receive an indication of a pipeline flush; and responsive to receiving the indication of the pipeline flush, invalidate one or more of the one or more entries of the early register cache.

7 . The apparatus of claim 1 , wherein at least one entry of the one or more entries of the early register cache is configured to store a narrow-width operand.

8 . The apparatus of claim 1 , wherein the one or more entries of the early register cache corresponds to a subset of a plurality of architectural registers of the OOO processor.

9 . The apparatus of claim 1 integrated into an integrated circuit (IC).

10 . The apparatus of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

11 . An apparatus comprising an early execution engine of an out-of-order (OOO) processor, the early execution engine comprising:
a means for receiving an incoming instruction from a front-end instruction pipeline of the OOO processor; a means for determining whether an input operand of one or more input operands of the incoming instruction is present in a corresponding entry of one or more entries in an early register cache of the early execution engine; and a means for substituting the input operand with a non-speculative immediate value stored in the corresponding entry, responsive to determining that the input operand is present in the corresponding entry.

12 . A method for providing early instruction execution, comprising:
receiving, by an early execution engine of an out-of-order (OOO) processor, an incoming instruction from a front-end instruction pipeline of the OOO processor; determining whether an input operand of one or more input operands of the incoming instruction is present in a corresponding entry of one or more entries in an early register cache of the early execution engine; and responsive to determining that the input operand is present in the corresponding entry, substituting the input operand with a non-speculative immediate value stored in the corresponding entry.

13 . The method of claim 12 , further comprising, responsive to determining that the input operand is not present in the corresponding entry:
invalidating an entry of the early register cache corresponding to an output operand of the incoming instruction; and providing the incoming instruction as an outgoing instruction to a back-end instruction pipeline of the OOO processor for execution.

14 . The method of claim 12 , further comprising:
determining whether the incoming instruction is an early-execution-eligible instruction; and responsive to determining that the incoming instruction is the early-execution-eligible instruction:
executing the early-execution-eligible instruction using an early execution unit of the early execution engine;
writing an output value of the early-execution-eligible instruction to an entry of the early register cache corresponding to an output operand of the early-execution-eligible instruction; and
providing an outgoing instruction to a back-end instruction pipeline of the OOO processor for execution.

15 . The method of claim 14 , further comprising, responsive to determining that the incoming instruction is not the early-execution-eligible instruction:
invalidating the entry of the early register cache corresponding to the output operand of the incoming instruction; and providing the incoming instruction as the outgoing instruction to the back-end instruction pipeline for execution.

16 . The method of claim 12 , further comprising:
receiving one or more architectural register values from the OOO processor, the one or more architectural register values corresponding to the one or more entries of the early register cache; and updating the one or more entries of the early register cache to store the one or more architectural register values.

17 . The method of claim 12 , further comprising:
receiving an indication of a pipeline flush; and responsive to receiving the indication of the pipeline flush, invalidating one or more of the one or more entries of the early register cache.

18 . The method of claim 12 , wherein at least one entry of the one or more entries of the early register c

Assignees

• Qualcomm Inc

Inventors

• Cain Iii Harold Wade
• Al Sheikh Rami Mohammad

Classifications

• G06F9/30138

  Extension of register space, e.g. register cache · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/3832

  Value prediction for operands; operand history buffers · CPC title