Physical layout features of integrated circuit device to enhance optical failure analysis
US-2015380325-A1 · Dec 31, 2015 · US
US9535025B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9535025-B2 |
| Application number | US-201314382599-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 6, 2013 |
| Priority date | Mar 6, 2012 |
| Publication date | Jan 3, 2017 |
| Grant date | Jan 3, 2017 |
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A probe assembly includes plural capacitive contacts that are separate from each other and a conductive depletion gate disposed between and separating the contacts from each other. The depletion gate is configured to receive a direct electric voltage to deplete regions of a sample under test of electrons. The contacts are configured to be placed in close proximity to a buried conducting layer in the sample under test without engaging the buried conducting layer, thereby capacitively coupling to the buried conducting layer. A first subset of the capacitive contacts is configured to apply an alternating electric current to a portion of the sample under test and a second subset of the capacitive contacts is configured to sense an alternating voltage response of the portion of the sample under test to characterize one or more electrical properties of the sample under test without the capacitive contact with the buried conductive layer.
Opening claim text (preview).
The invention claimed is: 1. A probe assembly comprising: plural conductive capacitive contacts that are separate from each other; and a conductive depletion gate disposed between and separating the capacitive contacts from each other, the depletion gate configured to receive an electric voltage in order to deplete regions of a sample under test of electrons, the sample under test includes a semiconductor or insulator body having a buried conducting layer, wherein the capacitive contacts are configured to be placed in close proximity to the buried conducting layer in the sample under test without engaging the buried conducting layer, a first subset of the capacitive contacts configured to apply an alternating electric current to a portion of the sample under test and a second subset of the capacitive contacts configured to sense an alternating voltage response of the portion of the sample under test in order to characterize one or more electrical properties of the sample under test without the capacitive contacts having ohmic contact with the buried conducting layer. 2. The probe assembly of claim 1 , wherein the first subset of the capacitive contacts is configured to apply the alternating electric current and the second subset of the capacitive contacts is configured to sense the alternating voltage response of the portion of the sample under test in order to determine at least one of a sheet resistance or a charge carrier mobility or a charge carrier density of the portion of the semiconductor or insulator sample under test. 3. The probe assembly of claim 2 , wherein the first subset of the capacitive contacts includes first and second neighboring capacitive contacts and the second subset of the capacitive contacts includes third and fourth neighboring capacitive contacts. 4. The probe assembly of claim 1 , wherein the first subset of the capacitive contacts is configured to apply the alternating electric current and the second subset of the capacitive contacts is configured to sense the alternating voltage response of the portion of the sample under test while the sample under test is exposed to a magnetic field oriented perpendicular to a surface of the sample under test that faces the capacitive contacts in order to determine at least one of a Hall resistance or a charge carrier density of the portion of the sample under test. 5. The probe assembly of claim 4 , wherein the first subset of the capacitive contacts includes non-neighboring first and third capacitive contacts and the second subset of the capacitive contacts includes non-neighboring second and fourth capacitive contacts. 6. The probe assembly of claim 1 , wherein the depletion gate includes separation fingers that extend between and separate the capacitive contacts from each other. 7. The probe assembly of claim 1 , wherein the depletion gate extends between the capacitive contacts and at least partially around a region under test between the capacitive contacts, the region under test representing an area that faces an undepleted region of the sample under test, the depletion gate including openings between the region under test and the capacitive contacts that permit the electric current applied by the first subset of capacitive contacts to be at least partially conducted through the undepleted region of the sample under test. 8. The probe assembly of claim 1 , wherein the depletion gate includes conductive fingers that extend between the capacitive contacts and separate the capacitive contacts from each other, the conductive fingers defined by an outer width dimension, wherein the capacitive contacts are in close proximity to the buried conducting layer when the capacitive contacts are separated from the buried conducting layer by a distance that is as small or smaller than the outer width dimension of the conductive fingers. 9. A method comprising: positioning a probe assembly in close proximity to a buried conducting layer in a sample under test, the probe assembly having plural conductive capacitive contacts that are separate from each other and a conductive depletion gate disposed between and separating the capacitive contacts from each other, the sample under test including a semiconductor or insulator body having a buried conducting layer; supplying the depletion gate with a direct electric voltage in order to deplete regions of the sample under test of electrons; conducting an alternating electric current through a first subset of the capacitive contacts to a portion of the sample under test; and sensing an alternating voltage response of the portion of the sample under test in response to the second alternating electric current being conducted through the first subset of the capacitive contacts in order to characterize one or more electrical properties of the sample under test without the contacts having ohmic contact with the buried conducting layer. 10. The method of claim 9 , further comprising determining at least one of a sheet resistance or a charge carrier mobility of the portion of the sample under test using the alternating voltage response that is sensed. 11. The method of claim 10 , wherein the alternating electric current is conducted through first and second capacitive contacts that neighbor each other and the alternating voltage response is sensed using third and fourth capacitive contacts that neighbor each other. 12. The method of claim 9 , further comprising exposing the sample under test to a magnetic field oriented perpendicular to a surface of the sample under test that faces the capacitive contacts, wherein determining at least one of a Hall resistance or a charge carrier density of the portion of the sample under test using the alternating voltage response that is sensed and the magnetic field. 13. The method of claim 12 , wherein the alternating electric current is conducted through non-neighboring first and third capacitive contacts and the voltage response is sensed using non-neighboring second and fourth capacitive contacts. 14. The method of claim 9 , wherein supplying the depletion gate with the first direct electric voltage depletes the regions of the sample under test of electrons between the capacitive contacts. 15. A probe assembly comprising: conductive capacitive contacts separated from each other and arranged around a region under test, the contacts configured to be positioned proximate to a sample under test, the sample under test including a semiconductor or insulator body having a buried conducting layer, the capacitive contacts configured to be positioned proximate to the sample under test without contacting the buried conducting layer, wherein a first subset of the capacitive contacts is configured to inject an alternating current into the sample under test outside of a portion of the sample under test that faces the region under test between the capacitive contacts, and wherein a different, second subset of the capacitive contacts is configured to sense an alternating voltage response of the portion of the sample under test in response to the alternating current being injected into the sample under test, the voltage response indicative of at least one of a charge carrier mobility or a charge carrier density in the portion of the sample under test that faces the region under test. 16. The probe assembly of claim 15 , wherein the first subset of the capacitive contacts includes first and second neighboring capacitive contacts and the second subset of the contacts includes third and fourth neighboring capacitive contacts. 17. The probe assembly of claim 15 , wherein the
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