Printed wiring board and method for manufacturing printed wiring board

Patent metadata

Field	Value
Publication number	US-9532468-B2
Application number	US-201414549951-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 21, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.

First claim

What is claimed is:

1. A wiring board, comprising:
a first resin insulating layer;
a plurality of conductor pads formed on the first resin insulating layer and comprising a first conductor pad and a second conductor pad;
a second resin insulating layer formed on the first resin insulating layer such that the second resin insulating layer is covering the first conductor pad and the second conductor pad;
an outermost surface conductor wiring layer formed on the second resin insulating layer and comprising a first outermost surface conductor wiring layer and a second outermost surface conductor wiring layer;
a plurality of via conductors penetrating through the second resin insulating layer and comprising a first via conductor connecting the first outermost surface conductor wiring layer and the first conductor pad and a second via conductor connecting the second outermost surface conductor wiring layer and the second conductor pad; and
a solder resist layer formed on the second resin insulating layer such that the solder resist layer is covering the first outermost surface conductor wiring layer and has at least one opening portion exposing the second outermost surface conductor wiring layer,
wherein the first via conductor and the first outermost surface conductor wiring layer comprise a first main metal, and the second via conductor and the second outermost surface conductor wiring layer comprise a second main metal which is different from the first main metal of the first via conductor and first outermost surface conductor wiring layer.

2. A wiring board according to claim 1 , wherein the first main metal of the first outermost surface conductor wiring layer is copper, and the second main metal of the second outermost surface conductor wiring layer is a metal selected from the group consisting of nickel, chromium, zinc, tin and tungsten.

3. A wiring board according to claim 1 , wherein the first outermost surface conductor wiring layer comprises an electrolytic plated layer, and the second outermost surface conductor wiring layer comprises an electrolytic plated layer.

4. A wiring board according to claim 3 , wherein the first outermost surface conductor wiring layer and the second outermost surface conductor wiring layer include a common seed layer.

5. A wiring board according to claim 2 , wherein the second main metal of the second outermost surface conductor wiring layer is nickel and includes one of a Pd/Au layer and a Au layer formed on a surface of the second main metal of the second outermost surface conductor wiring layer.

6. A wiring board according to claim 5 , wherein the one of a Pd/Au layer and a Au layer formed on the surface of the second main metal of the second outermost surface conductor wiring layer is an electrolytic plated layer.

7. A wiring board according to claim 1 , wherein the first outermost surface conductor wiring layer has a thickness which is greater than a thickness of the second outermost surface conductor wiring layer.

8. A wiring board according to claim 1 , wherein the second outermost surface conductor wiring layer comprises a plurality of connection pads.

9. A wiring board according to claim 1 , wherein the second outermost surface conductor wiring layer comprises a plurality of connection pads positioned at a pitch of 20 μm to 100 μm.

10. A wiring board according to claim 1 , wherein the solder resist layer has a plurality of opening portions positioned such that the plurality of opening portions is exposing a plurality of pad portions of the first outermost surface conductor wiring layer.

11. A wiring board according to claim 2 , wherein the first outermost surface conductor wiring layer has a thickness which is greater than a thickness of the second outermost surface conductor wiring layer.

12. A wiring board according to claim 2 , wherein the second outermost surface conductor wiring layer comprises a plurality of connection pads.

13. A wiring board according to claim 1 , wherein the second outermost surface conductor wiring layer comprises a plurality of connection pads, and the solder resist layer has a plurality of opening portions positioned such that the plurality of opening portions is exposing a plurality of pad portions of the first outermost surface conductor wiring layer.

14. A wiring board according to claim 1 , wherein the second outermost surface conductor wiring layer comprises a plurality of connection pads positioned to mount an electronic component.

15. A wiring board according to claim 1 , wherein the first outermost surface conductor wiring layer has a thickness which is greater than a thickness of the second outermost surface conductor wiring layer, the second outermost surface conductor wiring layer comprises a plurality of connection pads, and the solder resist layer has a plurality of opening portions positioned such that the plurality of opening portions is exposing a plurality of pad portions of the first outermost surface conductor wiring layer.

16. A method for manufacturing a wiring board, comprising:
forming on a first resin insulating layer a plurality of conductor pads comprising a first conductor pad and a second conductor pad;
forming a second resin insulating layer on the first resin insulating layer such that the second resin insulating layer covers the first conductor pad and the second conductor pad;
forming in the second resin insulating layer a first opening portion and a second opening portion such that the first opening portion reaches the first conductor pad and the second opening portion reaches the second conductor pad;
forming a seed layer on a surface of the second resin insulating layer such that the seed layer is formed in the first opening portion and the second opening portion;
forming a first resist layer on the seed layer such that the first resist layer covers the second opening portion and exposes the first opening portion and the surface of the second resin insulating layer around the first opening portion;
applying electrolytic plating of a first main metal such that a first via conductor comprising the first main metal is formed in the first opening portion and a first outermost surface conductor wiring layer comprising the first main metal is formed on an exposed portion of the second resin insulating layer;
removing the first resist layer from the second resin insulating layer;
forming a second resist layer such that the second resist layer covers the first outermost surface conductor wiring layer and exposes the second opening portion in the second resin insulating layer and a patterned portion of the surface of the second resin insulating layer around the second opening portion;
applying electrolytic plating of a second main metal such that a second via conductor comprising the second main metal is formed in the second opening portion and a second outermost surface conductor wiring layer comprising the second main metal is formed on the patterned portion of the second resin insulating layer;
removing the second resist layer from the second resin insulating layer;
removing a portion of the seed layer exposed from the first outermost surface conductor wiring layer and the second outermost surface conductor wiring layer; and
forming a solder resist layer such that the solder resist layer covers the first outermost surface conductor wiring layer and has at least one opening portion exposing the second outermost surface conductor wiring layer,
wherein the second main metal of the second via conductor and second outermost surface conductor wiring layer is different from the first main metal

Assignees

• Ibiden Co Ltd

Inventors

• Kunieda Masatoshi
• Terui Makoto
• Tominaga Ryoujiro
• Kariya Takashi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H05K2201/09736

  Varying thickness of a single conductor; Conductors in the same plane having different thicknesses · CPC title

• H05K1/114

  Pad being close to via, but not surrounding the via · CPC title

• H05K2201/0769

  Anti metal-migration, e.g. avoiding tin whisker growth · CPC title

• H05K2203/1394

  Covering open PTHs, e.g. by dry film resist or by metal disc · CPC title