Methods of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-9530870-B2
Application number	US-201514805876-A
Country	US
Kind code	B2
Filing date	Jul 22, 2015
Priority date	Jul 25, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., <111> and any other direction) of the semiconductor substrate.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate;
forming an active pattern that protrudes from the semiconductor substrate;
forming a gate pattern on the semiconductor substrate to cross the active pattern;
forming spacers on sidewalls of the gate pattern;
injecting amorphization elements into the active pattern to form amorphous portions in the active pattern at both sides of the gate pattern;
etching the amorphous portions to form recess regions in the active pattern; and
forming epitaxial patterns in the recess regions;
wherein each of the recess regions comprises:
a bottom surface having a {100} crystal plane;
side surfaces having a {110} crystal plane;
lower inclined surfaces having a {111} crystal plane and being provided between the bottom surface and the side surfaces; and
upper inclined surfaces having a {111} crystal plane and being provided on the side surfaces.

2. The method of claim 1 , wherein a vertical length of respective ones of the side surfaces is longer than a distance between both ends of respective ones of the lower inclined surfaces, and
the both ends of respective ones of the lower inclined surfaces meet the side and bottom surfaces, respectively.

3. The method of claim 1 , wherein the etching of the amorphous portions is performed in such a way that an etch rate of the amorphous portions is substantially the same in <111> and <100> directions of the semiconductor substrate.

4. The method of claim 1 , wherein the etching of the amorphous portions is performed in such a way that an etch rate of the amorphous portions is substantially the same in <111> and <110> directions of the semiconductor substrate.

5. The method of claim 1 , wherein, in each of the recess regions, the lower inclined surfaces are connected to each other through the bottom surface interposed therebetween.

6. The method of claim 1 , wherein, in each of the recess regions, the upper inclined surfaces are connected to the lower inclined surfaces through the side surfaces interposed therebetween.

7. The method of claim 1 , wherein the forming of the recess regions in the active pattern comprises:
forming preliminary recess regions in the active pattern at both sides of the gate pattern, the preliminary recess regions having side surfaces extending along side surfaces of the spacers; and
anisotropically etching the preliminary recess regions to increase widths of the preliminary recess regions.

8. The method of claim 1 , wherein the epitaxial patterns contain a same element as the amorphization elements.

9. The method of claim 8 , wherein the amorphization elements comprises germanium.

10. A method of fabricating a semiconductor device, comprising:
forming a gate pattern on a semiconductor substrate;
forming a spacer on a sidewall of the gate pattern;
forming a recess region in the semiconductor substrate at a side of the spacer; and
forming a source/drain pattern in the recess region,
wherein the forming of the recess region comprises:
etching the semiconductor substrate using the gate pattern and the spacer as a mask to form a first recess region;
injecting an amorphization element through the first recess region to form an amorphous portion in the semiconductor substrate; and
removing the amorphous portion to form a second recess region having a volume greater than that of the first recess region;
wherein the second recess region comprises:
a bottom surface having a {100} crystal plane;
a side surface having a {110} crystal plane;
a lower inclined surface having a {111} crystal plane and being provided between the bottom and side surfaces; and
an upper inclined surface having a {111} crystal plane and being provided on the side surface.

11. The method of claim 10 , wherein the amorphization element comprises germanium.

12. The method of claim 11 , wherein the injecting of the amorphization element is performed at a dose ranging from about 1×10 11 atoms/cm 2 to about 1×10 17 atoms/cm 2 .

13. The method of claim 10 , wherein the forming of the source/drain pattern comprises growing an epitaxial pattern from the semiconductor substrate exposed by the recess region, and the source/drain pattern comprises a same element as the amorphization element.

14. A method of fabricating a semiconductor device, comprising:
forming a pair of gate patterns on a semiconductor substrate;
forming spacers on sidewalls of the gate patterns;
forming an amorphous portion in the semiconductor substrate between the gate patterns;
performing a first etching procedure to form a first recess region in the amorphous portion such that a distance between the spacers on the respective gate patterns is about equal to a width of the first recess region; and performing a second etching procedure to form a second recess region by removing the amorphous portion that remains after the first etching procedure such that the distance between the spacers on the respective gate patterns is less than a width of the second recess region;
wherein the performing the second etching procedure comprises forming the second recess region in a space between the spacers on the respective gate patterns and the semiconductor substrate,
wherein the second recess region comprises:
a bottom surface;
side surfaces;
lower inclined surfaces between the bottom surface and side surfaces; and
upper inclined surfaces on the side surfaces.

15. The method of claim 14 , wherein the second etching procedure is performed in such a way that an etch rate of the amorphous portion is substantially the same in <111> and <100> directions of the semiconductor substrate.

16. The method of claim 14 , wherein the etching of the second etching procedure is performed in such a way that an etch rate of the amorphous portion is substantially the same in <111> and <110> directions of the semiconductor substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Jieon
• Kim Seokhoon
• Kim Gyeom
• Kim Nam-Kyu
• Kim Jinbum
• Suh Dong Chan
• Lee Kwan Heum
• Lee Byeongchan
• Lee Choeun
• Jung Sujin

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P95/906

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title