Semiconductor device and manufacturing method of same

Patent metadata

Field	Value
Publication number	US-9530859-B2
Application number	US-201314086301-A
Country	US
Kind code	B2
Filing date	Nov 21, 2013
Priority date	Nov 27, 2012
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.

First claim

What is claimed is:

1. A manufacturing method for a semiconductor device that includes a drift layer of a first conductivity type; a body layer of a second conductivity type that contacts a front surface of the drift layer, and a portion of which is exposed on a front surface of a semiconductor substrate; an emitter layer of the first conductivity type that is provided on a portion of a front surface of the body layer, and is exposed on the front surface of the semiconductor substrate, and that is separated from the drift layer by the body layer; a buffer layer of the first conductivity type that contacts a back surface of the drift layer; a collector layer of the second conductivity type that contacts a back surface of the buffer layer and is exposed on a back surface of the semiconductor substrate; and a gate electrode that faces, via an insulating film, the body layer in an area where the body layer separates the emitter layer from the drift layer, the manufacturing method comprising:
preparing a semiconductor wafer that includes (1) a first layer that is a monocrystalline silicon substrate, and (2) a second layer that is a polysilicon layer or an amorphous silicon layer, is layered on a back surface of the first layer, and has a higher polycrystalline silicon concentration than the first layer;
forming, in the second layer, the buffer layer by implanting and diffusing ions of the first conductivity type; and
forming in the second layer, the collector layer by implanting ions of the second conductivity type such that the collector layer contacts the back surface of the buffer layer.

2. The manufacturing method for a semiconductor device according to claim 1 , wherein the first layer includes a layer that has the drift layer, the body layer, and the emitter layer, and on which the gate electrode is formed.

3. A manufacturing method for a semiconductor device that includes a drift layer of a first conductivity type; a body layer of a second conductivity type that contacts a front surface of the drift layer, and a portion of which is exposed on a front surface of a semiconductor substrate; an emitter layer of the first conductivity type that is provided on a portion of a front surface of the body layer, and is exposed on the front surface of the semiconductor substrate, and that is separated from the drift layer by the body layer; a buffer layer of the second conductivity type that contacts a back surface of the drift layer; a collector layer of the first conductivity type that contacts a back surface of the buffer layer and is exposed on a back surface of the semiconductor substrate; and a gate electrode that faces, via an insulating film, the body layer in an area where the body layer separates the emitter layer from the drift layer, the manufacturing method comprising:
preparing a semiconductor wafer that includes (1) a first layer that is a monocrystalline silicon substrate and that has the drift layer, the body layer, and the emitter layer, and on which the gate electrode is formed, and (2) a second layer that is a polysilicon layer or an amorphous silicon layer, is formed by noble gas ion implantation on a back surface of the first layer, and has a higher polycrystalline silicon concentration than the first layer;
forming, in the second layer, the buffer layer by implanting and diffusing impurity ions of a first conductivity type; and
forming, in the second layer, the collector layer by implanting ions of the second conductivity type such that the collector layer contacts the back surface of the buffer layer.

Assignees

• Oki Shuhei
• Nishiwaki Tsuyoshi
• Toyota Motor Co Ltd

Inventors

• Oki Shuhei
• Nishiwaki Tsuyoshi

Classifications

• H10D62/60

  Impurity distributions or concentrations · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D12/038 Primary

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H01L29/66348 Primary

  Electricity · mapped topic

• H01L29/36

  Electricity · mapped topic