Semiconductor arrangement with active drift zone

Patent metadata

Field	Value
Publication number	US-9530764-B2
Application number	US-201314372774-A
Country	US
Kind code	B2
Filing date	Jan 30, 2013
Priority date	Jan 31, 2012
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

First claim

The invention claimed is:

1. A semiconductor device arrangement, comprising:
a first semiconductor device having a load path;
a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal;
wherein the second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device;
wherein each of the second semiconductor devices has its control terminal connected either to one of the first and second load terminals of one of the other second semiconductor devices or to one load terminal of the first semiconductor device;
wherein each of the second semiconductor devices has at least one device characteristic; and
wherein at least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

2. The semiconductor device arrangement of claim 1 , wherein the second semiconductor devices are MOSFETs, MISFETs, MESFETs, FINFETs, JFETs, HEMTs, IGBTs or nanotube devices and wherein the at least one device characteristic is selected from: a gate resistance; a threshold voltage; a gate-source capacitance; a gate-drain capacitance; a drain-source capacitance; a channel width; a body thickness; a channel length; a gate oxide thickness;
and a doping concentration of one a source region, a body region and a drain region.

3. The semiconductor device arrangement of claim 1 , wherein the first semiconductor device is a transistor.

4. The semiconductor device arrangement of claim 3 , wherein the transistor is a normally-off transistor.

5. The semiconductor device arrangement of claim 1 , wherein the second semiconductor devices are normally-on transistors.

6. The semiconductor device arrangement of claim 1 ,
wherein one of the second semiconductor devices that has its load path directly connected to the load path of the first semiconductor device has its control terminal connected to a first load terminal of the first semiconductor device; and
wherein each of the other second semiconductor devices has its control terminal connected to a first load terminal of another second semiconductor device.

7. The semiconductor device arrangement of claim 6 , wherein each of the other second semiconductor devices has its control terminal connected to a first load terminal of an adjacent second semiconductor device.

8. The semiconductor device arrangement of claim 6 , wherein a resistor is connected between the control terminal of the at least one second semiconductor device and the first load terminal of another second semiconductor device.

9. The semiconductor device arrangement of claim 8 , wherein a rectifier element is connected in parallel with the resistor.

10. The semiconductor device arrangement of claim 1 , wherein a capacitor is connected between the control terminal and the first load terminal of the at least one second semiconductor device, the capacitor being additionally to a gate-source capacitance of the at least one second semiconductor device.

11. The semiconductor device arrangement of claim 1 , wherein the first semiconductor device is one of an n-channel or p-channel transistor.

12. The semiconductor device arrangement of claim 11 , wherein the second semiconductor devices are one of n-channel or p-channel transistors.

13. The semiconductor device arrangement of claim 1 , wherein the second semiconductor devices are FINFETs, each comprising:
at least one semiconductor fin;
a source region, a body region and a drain region arranged in the at least one semiconductor fin, with the body region being arranged between the source region and the drain region; and
a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.

14. A semiconductor device arrangement, comprising:
a first semiconductor device having a load path;
a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal, wherein the second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device, thereby forming a first series circuit, wherein the first series circuit is connected between a first load terminal and a second load terminal of the semiconductor device arrangement, and wherein each of the second semiconductor devices having its control terminal connected either to the load terminal of one of the other second semiconductor devices or to one of the load terminals of the first semiconductor device such that one of the second semiconductor devices receives as a drive voltage between its control terminal and one of its first and second load terminals a load path voltage of the first semiconductor device, and the other second semiconductor devices each receive as a drive voltage the load path voltage of at least one second semiconductor device;
a tap of the first series circuit, the tap located between the load paths of two of the second semiconductor devices;
a fuse; and
a third load terminal connected to the second load terminal and coupled to the tap via the fuse.

15. The semiconductor device arrangement of claim 14 , further comprising:
a switching element connected between the third load terminal and the tap, wherein the third load terminal is connected to the second load terminal.

16. The semiconductor device arrangement of claim 15 , wherein the switching element is a mechanical switching element, or a semiconductor switching element.

17. The semiconductor device arrangement of claim 14 , wherein each of the second semiconductor devices except for a first one of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and wherein the first one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.

18. A semiconductor device arrangement, comprising:
at least two series circuits connected in parallel, each series circuit comprising a first semiconductor device having a load path and a control terminal and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal;
a drive terminal;
at least one resistor connected between the control terminal of the first semiconductor device of one series circuit and the drive terminal;
wherein the second semiconductor devices of each series circuit have their load paths connected in series and connected in series to the load path of the first semiconductor device,
wherein each of the second semiconductor devices of each series circuit has its control terminal connected either to the load terminal of one of the other second semiconductor devices or to one of the load terminals of the first semiconductor device.

19. The semiconductor device arrangement of claim 18 , wherein each of the control terminals of the first semiconductor devices is coupled to the drive terminal via a resistor, wherein at least two of these resistors are different.

20. The semiconductor device arrangement of claim 18 , wherein the at least one resistor is part of an RC element.

21. The semiconductor device arrangement of claim 18 , wherein each of the control terminals of the first semiconductor devices is

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Weis Rolf
• Treu Michael
• Deboy Gerald
• Willmeroth Armin
• Weber Hans

Classifications

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D86/01 Primary

  Manufacture or treatment · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title