3D integrated circuit package with through-mold first level interconnects

Patent metadata

Field	Value
Publication number	US-9530758-B2
Application number	US-201514750811-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Dec 22, 2011
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.

First claim

What is claimed is:

1. A method of fabricating a semiconductor die pair, the method comprising:
bonding an active side of each of a plurality of singulated first dies to an active side of a corresponding one of a plurality of second dies on a wafer to form wafer-level first and second die pairs, each of the plurality of singulated first dies smaller in area than the corresponding one of the plurality of second dies;
forming a molding layer above the wafer-level first and second die pairs;
grinding the molding layer to expose each of the plurality of singulated first dies and interconnect bumps of each of the plurality of second dies; and
subsequent to grinding the molding layer, singulating the first and second die pairs to form a plurality of singulated first and second die pairs, wherein forming the plurality of singulated first and second die pairs comprises forming each singulated first and second die pair comprising a first semiconductor die having an active side with a surface area, the first semiconductor die comprising no through silicon vias (TSVs), and a second semiconductor die having an active side with a surface area larger than the surface area of the first semiconductor die, the active side of the first semiconductor die facing and conductively coupled to the active side of the second semiconductor die, and the second semiconductor die comprising interconnects that bypass, and are adjacent to, the first semiconductor die, wherein the interconnects of the second semiconductor die of each of the plurality of singulated first and second die pairs comprise a plurality of bumps that extend from the active side of the second semiconductor die, and are at least partially adjacent to the first semiconductor die, and further to a plurality of solder balls, and wherein the first semiconductor die, the plurality of bumps, and the plurality of solder balls are housed in the molding layer.

2. The method of claim 1 , wherein the second semiconductor die of each of the plurality of singulated first and second die pairs is configured to provide power to the corresponding first semiconductor die of each of the plurality of singulated first and second die pairs.

3. The method of claim 1 , further comprising:
grinding a back side of the wafer.

4. The method of claim 1 , wherein singulating the first and second die pairs comprises laser scribing a front side of the wafer.

5. The method of claim 4 , wherein singulating the first and second die pairs further comprises grinding a back side of the wafer subsequent to scribing the front side of the wafer.

6. A method of fabricating a semiconductor die pair, the method comprising:
bonding an active side of each of a plurality of singulated first dies to an active side of a corresponding one of a plurality of second dies on a wafer to form wafer-level first and second die pairs, each of the plurality of singulated first dies smaller in area than the corresponding one of the plurality of second dies;
forming a molding layer above the wafer-level first and second die pairs;
grinding the molding layer to expose each of the plurality of singulated first dies and interconnect bumps of each of the plurality of second dies; and
subsequent to grinding the molding layer, singulating the first and second die pairs to form a plurality of singulated first and second die pairs, wherein forming the plurality of singulated first and second die pairs comprises forming each singulated first and second die pair comprising a first semiconductor die having an active side with a surface area, the first semiconductor die comprising no through silicon vias (TSVs), and a second semiconductor die having an active side with a surface area larger than the surface area of the first semiconductor die, the active side of the first semiconductor die facing and conductively coupled to the active side of the second semiconductor die, and the second semiconductor die comprising interconnects that bypass, and are adjacent to, the first semiconductor die, wherein the interconnects of the second semiconductor die of each of the plurality of singulated first and second die pairs comprise a plurality of bumps that extend from the active side of the second semiconductor die, but not adjacent to the first semiconductor die, and further to a plurality of solder balls, and wherein the first semiconductor die, the plurality of bumps, and the plurality of solder balls are housed in the molding layer.

7. The method of claim 6 , wherein the second semiconductor die of each of the plurality of singulated first and second die pairs is configured to provide power to the corresponding first semiconductor die of each of the plurality of singulated first and second die pairs.

8. The method of claim 6 , further comprising:
grinding a back side of the wafer.

9. The method of claim 6 , wherein singulating the first and second die pairs comprises laser scribing a front side of the wafer.

10. The method of claim 9 , wherein singulating the first and second die pairs further comprises grinding a back side of the wafer subsequent to scribing the front side of the wafer.

11. A method of fabricating a semiconductor die pair, the method comprising:
bonding an active side of each of a plurality of singulated first dies to an active side of a corresponding one of a plurality of second dies on a wafer to form wafer-level first and second die pairs, each of the plurality of singulated first dies smaller in area than the corresponding one of the plurality of second dies;
forming a molding layer above the wafer-level first and second die pairs;
grinding the molding layer to expose each of the plurality of singulated first dies and interconnect bumps of each of the plurality of second dies; and
subsequent to grinding the molding layer, singulating the first and second die pairs to form a plurality of singulated first and second die pairs, wherein forming the plurality of singulated first and second die pairs comprises forming each singulated first and second die pair comprising a first semiconductor die having an active side with a surface area, the first semiconductor die comprising no through silicon vias (TSVs), and a second semiconductor die having an active side with a surface area larger than the surface area of the first semiconductor die, the active side of the first semiconductor die facing and conductively coupled to the active side of the second semiconductor die, and the second semiconductor die comprising interconnects that bypass, and are adjacent to, the first semiconductor die, wherein the interconnects of the second semiconductor die of each of the plurality of singulated first and second die pairs comprise a plurality of bump columns that extend from the active side of the second semiconductor die and adjacent to the first semiconductor die, the plurality of bump columns comprising intermediate solder balls.

12. The method of claim 11 , wherein the first semiconductor die and the plurality of bump columns are housed in the molding layer.

13. The method of claim 11 , wherein the second semiconductor die of each of the plurality of singulated first and second die pairs is configured to provide power to the corresponding first semiconductor die of each of the plurality of singulated first and second die pairs.

14. The method of claim 11 , further comprising:
grinding a back side of the wafer.

15. The method of claim 11 , wherein singulating the first and second die pairs comprises laser scribing a front side of the wafer.

16. The method of claim 15 , wherein singulating the first and second die pairs further

Assignees

• Mallik Debendra
• Sankman Robert L
• Intel Corp

Inventors

• Mallik Debendra
• Sankman Robert L

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/0198

  batch processes · CPC title