Chip package and chip assembly

Patent metadata

Field	Value
Publication number	US-9530754-B2
Application number	US-201514880373-A
Country	US
Kind code	B2
Filing date	Oct 12, 2015
Priority date	Sep 17, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

First claim

What is claimed is:

1. A chip package, comprising:
an electrically conductive carrier;
at least one first chip, the first chip comprising a first side and a second side opposite the first side, with its second side being electrically contacted to the electrically conductive carrier;
an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip;
at least one second chip over the insulating layer;
encapsulating material over the first chip and the second chip; and
electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip,
wherein the second chip is arranged next to the first chip.

2. The chip package according to claim 1 ,
wherein the insulating layer is formed over the whole first side of the first chip.

3. The chip package according to claim 1 ,
wherein the whole second chip is arranged over the insulating layer.

4. The chip package according to claim 1 ,
wherein a thickness of the insulating layer over the carrier and a thickness of the insulating layer over the first chip is the same or in a similar range.

5. The chip package according to claim 1 ,
wherein the material of the insulating layer comprises at least one of a ceramic, an inorganic type and a polymer.

6. The chip package according to claim 1 ,
wherein the first chip is a power chip.

7. The chip package according to claim 1 ,
wherein the second chip is an integrated circuit.

8. A chip assembly, comprising:
a carrier;
at least one first chip, the first chip comprising a first side and a second side opposite the first side, with its second side being arranged on the carrier and with the first chip being electrically contacted with the carrier;
a coating over at least a part of the carrier and over at least a part of the first side of the chip, the coating isolating the corresponding parts of the carrier and the first chip;
at least one second chip over the coating;
encapsulating material over the first chip and the second chip, wherein electrical contacts extend through the encapsulation material to at least one contact of the first chip and to at least one contact of the second chip; and
wherein the second chip is arranged next to the first chip.

9. The chip assembly according to claim 8 ,
wherein the second chip is arranged beside the first chip in a direction parallel to the first side of the first chip.

10. The chip assembly according to claim 8 ,
wherein the coating is formed over the whole first side of the first chip.

11. The chip assembly according to claim 8 ,
wherein the whole second chip is arranged over the coating.

12. The chip assembly according to claim 8 ,
wherein a thickness of the coating over the carrier and a thickness of the coating over the first chip are the same or in a similar range.

13. The chip assembly according to claim 8 ,
wherein the material of the coating comprises at least one of a ceramic, an inorganic type and a polymer.

Assignees

• Infineon Technologies Ag

Inventors

• Hosseini Khalil
• Mahler Joachim
• Kalz Franz-Peter
• Voelter Joachim
• Wombacher Ralf

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title