Semiconductor module

Patent metadata

Field	Value
Publication number	US-9530707-B2
Application number	US-201514877389-A
Country	US
Kind code	B2
Filing date	Oct 7, 2015
Priority date	Oct 3, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate.

First claim

What is claimed is:

1. A semiconductor module, comprising:
a printed circuit board having
an insulating plate,
a first wiring layer and a fourth wiring layer disposed on a principal surface of the insulating plate,
a second wiring layer and a third wiring layer disposed on a surface opposite to the principal surface,
a first via disposed in the insulating plate, and electrically and mechanically connected to the first wiring layer and third wiring layer, and
a second via disposed in the insulating plate, and electrically and mechanically connected to the second wiring layer and the fourth wiring layer;

a first insulating substrate disposed facing the first wiring layer, and having a first circuit plate on a surface facing the first wiring layer and the fourth wiring layer;
a second insulating substrate disposed facing the second wiring layer, and having a second circuit plate facing the second wiring layer and a third circuit plate facing the third wiring layer;
a first semiconductor chip sandwiched between the first wiring layer and the first circuit plate, and having a conductive joining material on two surfaces to fix to the first wiring layer and the first circuit plate;
a second semiconductor chip sandwiched between the second wiring layer and the second circuit plate, and having a conductive joining material on two surfaces to fix to the second wiring layer and second circuit plate;
a first heat release member sandwiched and fixed between the third wiring layer and the third circuit plate; and
a second heat release member sandwiched and fixed between the fourth wiring layer and the first circuit plate.

2. The semiconductor module according to claim 1 , wherein the first via on the insulating plate has an area of 10% or more relative to an area of the first semiconductor chip.

3. The semiconductor module according to claim 1 , wherein the second via on the insulating plate has an area of 10% or more relative to an area of the second semiconductor chip.

4. The semiconductor module according to claim 1 , wherein the first heat release member and the second heat release member are a conductive joining material or a metal plate.

5. The semiconductor module according to claim 1 , wherein the second circuit plate and the third circuit plate are integrally formed, and the first heat release member is formed from a high thermal conductive insulator.

6. The semiconductor module according to claim 1 , further comprising a metal plate disposed on a surface, of the second insulating substrate, opposite to a surface disposed with the second circuit plate.

7. The semiconductor module according to claim 1 , further comprising a metal plate disposed on a surface, of the first insulating substrate, opposite to the surface disposed with the first circuit plate.

8. The semiconductor module according to claim 1 , wherein the first via and the second via are columnar conductors filled inside each of a plurality of through holes disposed in the insulating plate of the printed circuit board.

9. The semiconductor module according to claim 1 , wherein each of the joining materials and heat release members is a solder.

10. The semiconductor module according to claim 1 , further comprising an external terminal electrically connected to the first wiring layer or second wiring layer.

Assignees

• Fuji Electric Co Ltd

Inventors

• Harada Takahito

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title