Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9530697-B1
Application number	US-201615050711-A
Country	US
Kind code	B1
Filing date	Feb 23, 2016
Priority date	Sep 9, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor film, a memory film, an interconnect portion, and first and second insulating films. The first and second insulating films are provided on the interconnect portion. The interconnect portion includes first and second interconnect portions. The first interconnect portion is provided on the substrate. A width of a cross-section of the second interconnect portion decreases with increased distance from the substrate. The first insulating film is provided on side surfaces of the first and second interconnect portions. The second insulating film includes first to third portions. The first portion is provided on an upper surface of the interconnect portion. The first insulating film is provided between the second portion and the side surface of the second interconnect portion. The third portion extends in a second direction crossing the stacking direction and the first direction.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor memory device, comprising:
alternately stacking, on a substrate, an insulating layer and a first layer to form a stacked body;
forming, in the stacked body, a through-hole extending in a stacking direction of the stacked body;
forming, in the through-hole, a columnar portion including a memory film and a semiconductor film;
forming a first insulating layer on the stacked body and the columnar portion;
forming, in the stacked body and the first insulating layer, a trench extending in the stacking direction and a first direction crossing the stacking direction;
removing the first layer through the trench;
forming a conductive layer in a cavity resulting from the removal of the first layer through the trench;
forming a first insulating film in the trench;
forming a conductive film on the first insulating film in the trench;
removing a portion of the first insulating layer, a portion of the first insulating film, and a portion of the conductive film to form a plate-like interconnect portion including a protruding portion whose width in cross-section decreases with increased distance from the substrate;
forming a second insulating film on a side surface of the protruding portion; and
forming a third insulating film including a first portion provided on an upper surface of the interconnect portion, a second portion provided on the second insulating film, and a third portion extending in a second direction crossing the stacking direction and the first direction.

2. The method according to claim 1 , wherein
the first insulating film and the second insulating film are films containing silicon oxide, and
the third insulating film is a film containing silicon nitride.

3. The method according to claim 1 , comprising:
forming a second insulating layer on the first insulating layer;
removing a portion of the second insulating layer to form a contact hole; and
burying a conductor in the contact hole to form a first contact portion connecting with the semiconductor film.

4. The method according to claim 3 , wherein
the third portion protrudes toward the first contact portion.

5. The method according to claim 3 , wherein
the third insulating film is located in the second insulating layer.

6. The method according to claim 3 , further comprising removing a portion of the first portion to form a second contact portion connecting with the interconnect portion.

7. The method according to claim 6 , further comprising:
forming a first interconnect connecting with the first contact portion; and
forming a second interconnect connecting with the second contact portion.

8. A semiconductor memory device comprising:
a substrate;
a stacked body provided on the substrate and including a plurality of electrode layers separately stacked each other;
a semiconductor film extending in a stacking direction in the stacked body;
a memory film provided between the semiconductor film and one of the plurality of electrode layers;
a plate-like interconnect portion provided in the stacked body and extending in the stacking direction and a first direction crossing the stacking direction; and
a first insulating film and a second insulating film provided on the interconnect portion,
the interconnect portion including a first interconnect portion provided on the substrate and a second interconnect portion whose width in cross-section decreases with increased distance from the substrate,
the first insulating film being provided on a side surface of the first interconnect portion and a side surface of the second interconnect portion,
the second insulating film including a first portion, a second portion, and a third portion, the first portion being provided on an upper surface of the interconnect portion, the first insulating film being provided between the second portion and the side surface of the second interconnect portion, the third portion extending in a second direction crossing the stacking direction and the first direction.

9. The device according to claim 8 , wherein
the first insulating film is a film containing silicon oxide, and
the second insulating film is a film containing silicon nitride.

10. The device according to claim 8 , further comprising a first contact portion connecting with the semiconductor film, wherein
the third portion protrudes toward the first contact portion.

11. The device according to claim 8 , wherein
a distance in the stacking direction between the third portion and the stacked body is shorter than a distance in the stacking direction between the first portion and the stacked body,
the distance in the stacking direction between the third portion and the stacked body is shorter than a distance in the stacking direction between the second portion and the stacked body, and
the distance in the stacking direction between the second portion and the stacked body is shorter than the distance in the stacking direction between the first portion and the stacked body.

12. The device according to claim 8 , further comprising:
a first contact portion connecting with the semiconductor film; and
an insulating layer provided on the stacked body, wherein
the second insulating film and the first contact portion are provided in the insulating layer.

13. The device according to claim 8 , wherein
the first interconnect portion is provided such that a width in cross-section of the first interconnect portion increases with increased distance from the substrate, and
the second interconnect portion is provided on the first interconnect portion.

14. The device according to claim 8 , further comprising:
a first contact portion connecting with the semiconductor film;
a second contact portion connecting with the interconnect portion;
a first interconnect connected to the first contact portion; and
a second interconnect connected to the second contact portion.

Assignees

• Toshiba Kk

Inventors

• Nakaki Hiroshi

Classifications

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016 Primary

  the components including vertical IGFETs · CPC title

• H01L21/823487 Primary

  Electricity · mapped topic

• H01L27/11553

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic