Data processing device and data processing system

Patent metadata

Field	Value
Publication number	US-9529402-B2
Application number	US-201013818379-A
Country	US
Kind code	B2
Filing date	Sep 2, 2010
Priority date	Sep 2, 2010
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.

First claim

The invention claimed is:

1. A data processing device comprising:
a load circuit including a central processing unit and operated by a supplied electric power;
a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including:
a first step-down unit stepping down the external power supply voltage;
a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit; and
a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit,

wherein the bias current control circuit includes a first MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) including a source-drain path as the auxiliary path and a gate coupled to receive a first bias control signal from the control circuit,
wherein when the load circuit makes a first transition from a state of relatively high power consumption to a state of relatively low power consumption, the control circuit increases the magnitude of the bias current, prior to the first transition, by outputting the first level of the first bias control signal to the gate of the first MOSFET to turn on the first MOSFET,
wherein when the load circuit makes a second transition from a state of relatively low power consumption to a state of relatively high power consumption, the control circuit increases the magnitude of the bias current, prior to the second transition, by outputting the first level of the first bias control signal to the gate of the first MOSFET to turn on the first MOSFET, and
wherein after a predetermined time from each of the first transition and the second transition, the control circuit decreases the magnitude of the bias current by outputting a second level of the first bias control signal to the gate of the first MOSFET to turn off the first MOSFET.

2. The data processing device according to claim 1 , further comprising:
wherein the first step-down unit includes:
a differential operational amplifier amplifying a potential difference between a reference voltage and the output node;
an output transistor provided between the output node and an external power supply node and including a gate connected to an output of the differential operational amplifier; and
a second MOSFET including a source-drain path coupled between the output node and the ground and including a gate coupled to receive a second bias control signal from the control circuit,
wherein the control circuit provides a first level of the second bias control signal in the whole period of the state of relatively high power consumption as well as a starting period and an ending period of the state of relatively low power consumption to turn on the second MOSFET, and
provides a second level of the second bias control signal except for the starting and ending periods of the state of relatively low power consumption to turn off the second MOSFET.

3. The data processing device according to claim 2 , further comprising:
wherein the bias current control circuit further includes a third MOSFET including a source-drain path coupled in series to the source-drain path of the first MOSFET and including a gate coupled to receive the second bias control signal,
wherein the second MOSFET turns on by the first level of the second bias control signal and turns off the second level of the second bias control signal.

4. The data processing device according to claim 2 , further comprising:
wherein the bias current control circuit further includes a third MOSFET including a source-drain path coupled in series to the source-drain path of the first MOSFET and a gate coupled to the output node.

5. The data processing device according to claim 1 , further comprising:
wherein the load circuit includes a component operating at least in the state of relatively low power consumption,
wherein the step-down power supply circuit further includes a second step-down unit stepping down the external power supply voltage,
wherein the first step-down unit operates only in the state of relatively high power consumption, and
wherein the second step-down unit operates in the state of relatively high power consumption and the state of relatively low power consumption.

6. The data processing device according to claim 2 , further comprising:
wherein a current control by the control circuit is according to the first transition.

7. The data processing device according to claim 1 , further comprising:
wherein the central processing unit includes a processor, and the first step-down unit includes a first step-down circuit.

Assignees

• Kobayashi Soichi
• Oizumi Akira
• Yasu Yoshihiko
• Notani Hiromi
• Renesas Electronics Corp

Inventors

• Kobayashi Soichi
• Oizumi Akira
• Yasu Yoshihiko
• Notani Hiromi

Classifications

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/32 Primary

  Means for saving power · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title