Integrated circuit chip and a method for testing the same
US-9506986-B2 · Nov 29, 2016 · US
US9529046B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9529046-B2 |
| Application number | US-201414573975-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 17, 2014 |
| Priority date | Dec 12, 2014 |
| Publication date | Dec 27, 2016 |
| Grant date | Dec 27, 2016 |
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A method and apparatus are provided for isolating a defect in a scan chain comprising a plurality of components of an integrated circuit. A plurality of injection points may be positioned along the scan chain. Each injection point may be configured to introduce binary test data. A plurality of bypass structures may each be configured to selectively direct a flow of the binary test data to generate a plurality of partitioned scan paths. Test logic may be configured to execute a plurality of tests using the plurality of partitioned scan paths and to combine results of the plurality of tests to isolate a faulty component of the plurality of components.
Opening claim text (preview).
The invention claimed is: 1. An apparatus comprising: a scan chain comprising components of an integrated circuit; injection point structures positioned in the scan chain, wherein each injection point structure is configured to introduce binary test data at a respective point in the scan chain; bypass structures, wherein each bypass structure includes a corresponding input coupled to an output of one injection point structure in the scan chain, wherein an output of each bypass…
Physics · mapped topic
Physics · mapped topic
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