Integrated circuit chip and a method for testing the same

US9506986B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9506986-B2
Application numberUS-201414476883-A
CountryUS
Kind codeB2
Filing dateSep 4, 2014
Priority dateDec 6, 2013
Publication dateNov 29, 2016
Grant dateNov 29, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A chip comprising at least two integrated circuits, at least three scan chains, and a multiplexor circuitry, each integrated circuit comprising an input port and an output port, the scan chains and the integrated circuits are coupled in a series chain with the integrated circuits and the scan chains alternating each other, the series chain beginning with an initial scan chain and ending with an end scan chain, wherein each scan chain comprises a first scan ch…

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What does patent US9506986B2 cover?
An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G01R31/318544. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).