Two-dimensional scan architecture
US-9222978-B2 · Dec 29, 2015 · US
US9506986B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9506986-B2 |
| Application number | US-201414476883-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 4, 2014 |
| Priority date | Dec 6, 2013 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.
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What is claimed is: 1. A chip comprising at least two integrated circuits, at least three scan chains, and a multiplexor circuitry, each integrated circuit comprising an input port and an output port, the scan chains and the integrated circuits are coupled in a series chain with the integrated circuits and the scan chains alternating each other, the series chain beginning with an initial scan chain and ending with an end scan chain, wherein each scan chain comprises a first scan ch…
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