Integrated circuit package and method

US9527728B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9527728-B2
Application numberUS-201313947235-A
CountryUS
Kind codeB2
Filing dateJul 22, 2013
Priority dateJul 22, 2013
Publication dateDec 27, 2016
Grant dateDec 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming a packaged electronic device includes fabricating a MEMS structure, such as a BAW structure, on a first semiconductor wafer substrate; forming a cavity in a second semiconductor wafer substrate; and mounting the second substrate on the first substrate such that the MEMS structure is positioned inside the cavity in the second substrate. A wafer level assembly and an integrated circuit package are also described.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit package comprising: a first semiconductor substrate having a top surface and a bottom surface with a microelectromechanical system (MEMS) structure and at least one a contact pad formed on said top surface, said at least one contact pad being formed over a non-recessed portion of said top surface; a second semiconductor substrate having a top surface and a bottom surface and having a cavity with an opening in said bottom surface, wherein said bottom surface of said second semiconductor substrate is attached to said top surface of said first semiconductor substrate, and wherein said MEMS structure is positioned inside said cavity and said at least one contact pad is positioned outside said cavity; and a leadframe having a die attachment pad and at least one lead, wherein said first semiconductor substrate is mounted on said die attachment pad and wherein said at least one contact pad is attached by at least one bond wire to said at least one lead. 2. The integrated circuit package of claim 1 , wherein said first semiconductor substrate comprises a hole extending therethrough that exposes said MEMS structure. 3. The integrated circuit package of claim 1 further comprising a layer of encapsulant covering said first and second semiconductor substrates, said at least one bond wire, and at least a portion of said leadframe. 4. The integrated circuit package of claim 1 wherein said MEMS structure is a bulk acoustic wave (BAW) filter structure. 5. The integrated circuit package of claim 1 , comprising a die attachment film disposed between said die attachment pad and said first semiconductor substrate. 6. The integrated circuit package of claim 5 , wherein said die attachment film comprises an epoxy resin having a filler material. 7. The integrated circuit package of claim 1 , wherein a ratio of the height of the second semiconductor substrate to the height of the first semiconductor substrate is between approximately 3:1 to 10:1. 8. The integrated circuit package of claim 1 , wherein said top surface of the first semiconductor substrate on which said MEMS structure and said at least one contact pad are formed is substantially planar. 9. The integrated circuit package of claim 1 , wherein said MEMS structure is formed over a non-recessed portion of said top surface of said first semiconductor substrate. 10. The integrated circuit package of claim 1 , wherein said at least one contact pad has an uppermost surface that is not coplanar with the top surface of said first semiconductor substrate. 11. An integrated circuit package comprising: a die comprising: a first semiconductor substrate having a top surface and a bottom surface, wherein the top surface is substantially planar and the first semiconductor substrate comprises a microelectromechanical system (MEMS) structure formed on the top surface; and a second semiconductor substrate having a top surface and a bottom surface, wherein the second semiconductor substrate comprises a cavity formed in the bottom surface, wherein the bottom surface of the second semiconductor substrate is attached to the top surface of the first semiconductor substrate to enclose the MEMS structure inside the cavity, and wherein the die has a thickness of less than or equal to approximately 300 μm; and a leadframe comprising a die attachment pad, wherein the first semiconductor substrate is mounted on the die attachment pad. 12. The integrated circuit package of claim 11 , wherein the die comprises a contact pad formed on the top surface of the first semiconductor substrate adjacent to the MEMS structure, and wherein the leadframe comprises a lead, the contact pad being attached to the lead by a bond wire. 13. The integrated circuit package of claim 12 , wherein the contact pad is not enclosed within the cavity. 14. The integrated circuit package of claim 11 , wherein the die has a thickness of between approximately 200 μm to 300 μm. 15. The integrated circuit package of claim 11 , wherein the MEMS structure comprises a bulk acoustic wave (BAW) filter. 16. An integrated circuit die comprising; a first semiconductor substrate having a top surface and a bottom surface, wherein the top surface is substantially planar; a second semiconductor substrate having a top surface and a bottom surface, the bottom surface having a cavity formed therein, wherein the bottom surface of the second semiconductor substrate is attached to the top surface of the first semiconductor substrate to form an enclosure defined by the cavity; and a microelectromechanical system (MEMS) structure formed on the top surface of the first semiconductor substrate and enclosed within the enclosure; wherein the die has a thickness of less than or equal to approximately 300μm. 17. The integrated circuit die of claim 16 , comprising a contact pad formed on the top surface of the first semiconductor substrate, the contact pad not enclosed within the enclosure. 18. The integrated circuit die of claim 16 , wherein the die has a thickness of between approximately 200 μm to 300 μm. 19. The integrated circuit die of claim 16 , wherein the second semiconductor substrate does not comprise circuitry. 20. The integrated circuit package of claim 1 , wherein said at least one bond wire has a low loop configuration.

Assignees

Inventors

Classifications

  • Moulding a cap over the MEMS device · CPC title

  • Bonding of solid lids or wafers to the substrate · CPC title

  • Bonding a wafer on the substrate, i.e. where the cap consists of another wafer · CPC title

  • for obtaining desired frequency or temperature coefficients · CPC title

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Frequently asked questions

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What does patent US9527728B2 cover?
A method of forming a packaged electronic device includes fabricating a MEMS structure, such as a BAW structure, on a first semiconductor wafer substrate; forming a cavity in a second semiconductor wafer substrate; and mounting the second substrate on the first substrate such that the MEMS structure is positioned inside the cavity in the second substrate. A wafer level assembly and an integrate…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification B81C1/00269. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Dec 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).